公开(公告)号：US20030172363A1

公开(公告)日：2003-09-11

申请号：US10347139

申请日：2003-01-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: G06F017/50

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 提供了一种方法和改进的FPGA装置，用于在核心逻辑功能中使得能够选择性地部署IO单元中的未使用的触发器或其他电路元件以及查找表（LUT）中的未使用的解码器或其他电路元件，包括用于 有选择地从IO垫电路或所述LUT电路断开未使用的电路元件，以及连接装置，用于选择性地将所述断开的电路元件连接到核心逻辑的连接矩阵或它们之间，以提供独立配置的功能。

公开(公告)号：US20160126909A1

公开(公告)日：2016-05-05

申请号：US14530055

申请日：2014-10-31

Applicant: STMICROELECTRONICS PVT. LTD.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03F3/45 ,  H03K5/24

CPC classification number: H03F3/45179 ,  H03F2200/129 ,  H03F2203/45112 ,  H03F2203/45116 ,  H03K5/2481

Abstract: In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.

Abstract translation: 在一个实施例中，电路包括具有与第一晶体管和第二晶体管的差分对的差分放大器。 第一和第二晶体管中的每一个包括前门接触和后门接触。 第一数字反馈回路耦合在差分放大器的输出端与第一晶体管的后栅极接触之间。 第二数字反馈环耦合到第二晶体管的背栅极接触。 第一数字反馈回路被配置为与第二数字反馈回路相位相反。

公开(公告)号：US20140375357A1

公开(公告)日：2014-12-25

申请号：US13926748

申请日：2013-06-25

Applicant: STMicroelectronics (CROLLES 2) SAS ,  STMicroelectronics Pvt Ltd

Inventor： Vinod KUMAR ,  Pradeep Kumar BADRATHWAL ,  Saiyid Mohammad Irshad RIZVI ,  Paras GARG ,  Kallol CHATTERJEE ,  Pierre DAUTRICHE

IPC: H03K19/003

CPC classification number: H03K19/00384

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract translation: 具有集中PT补偿电路以向芯片上的局部I / O块提供补偿信号的电路。 整个集成电路芯片的工艺变化和温度变化趋向于大致均匀。 因此，与过去的解决方案一样，可以使用单个集中式PT补偿电路来代替每个I / O部分的一个PT补偿电路。 此外，PT补偿电路可以产生指示过程和温度的影响的数字代码。 此外，I / O块的每个部分可以具有用于补偿I / O块的电压变化的局部电压补偿电路。 电压补偿电路采用独立的参考电压。 参考电压由放置在IC芯片中央的PT补偿电路产生，因此不需要重复每个I / O块的参考生成。

公开(公告)号：US20130202031A1

公开(公告)日：2013-08-08

申请号：US13827210

申请日：2013-03-14

Applicant: STMICROELECTRONICS PVT. LTD. ,  STMICROELECTRONICS SRL

Inventor： Subarna TRIPATHI ,  Emiliano PICCINELLI

IPC: H04N7/26

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/124 ,  H04N19/146 ,  H04N19/149 ,  H04N19/152 ,  H04N19/162 ,  H04N19/169 ,  H04N19/177 ,  H04N19/40

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract translation: 独立于GOP的动态比特率控制器系统包括用于接收一个或多个输入参数的用户界面，比特率控制器和编码器。 比特率控制器调节输出比特流的比特率。 比特率控制器包括用于确定比特估计和量化参数的多个比特率模块，以及基于所接收的输入参数和帧速率来计算收敛周期的控制模块。 控制模块基于收敛周期选择比特率模块，并且编码器使用由比特率模块确定的量化参数来生成输出比特流。

公开(公告)号：US20130103865A1

公开(公告)日：2013-04-25

申请号：US13658667

申请日：2012-10-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Pvt. Ltd.

Inventor： Ignazio Antonino Urzi ,  Vivek Mohan Sharma

IPC: G06F3/00

CPC classification number: G06F13/387 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method for transmitting data on a configurable bus of z physical links, including receiving input data on an input bus at at least one of a plurality of data rates, selecting a number of physical links n, amongst the z physical links, on which data is to be transmitted, selecting a clock frequency f at which the data is to be transmitted on the configurable bus, wherein the selections of n and f are based on information concerning the at least one of the plurality of data rates, the number of links used on the input bus.

Abstract translation: 一种用于在z物理链路的可配置总线上发送数据的方法，包括以多个数据速率中的至少一个在输入总线上接收输入数据，在所述z个物理链路中选择数量的物理链路n， 将要发送的数据的时钟频率f选择在可配置总线上传送的时钟频率f，其中n和f的选择是基于与多个数据速率中的至少一个数据速率有关的信息，链路数量 用于输入总线。

公开(公告)号：US20040223364A1

公开(公告)日：2004-11-11

申请号：US10804562

申请日：2004-03-19

Applicant: STMICROELECTRONICS PVT. LTD.

Inventor： Rajeev Srivastavaan ,  Chiranjeev Grover

IPC: G11C015/00

CPC classification number: G11C15/00

Abstract: This invention provides, in an exemplary embodiment, a Content Addressable Memory (nullCAMnull) architecture providing improved speed by performing mutually exclusive operations in first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in the second state of the same clock cycles. The Content Addressable Memory (CAM) architecture comprises an array of CAM cells connected to a compare-data-write-driver and to a read/write block, for receiving the compare-data and for reading and/or writing data in the array of CAM cells respectively, outputs of the said CAM cell are coupled to a match block providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during first state and enabling read-or-write operations within the second state of the same clock cycle in the event of a match.

Abstract translation: 本发明在一个示例性实施例中提供了一种内容可寻址存储器（“CAM”）架构，其通过在时钟周期的第一状态下执行互斥操作并且依赖于至少一个先前的操作执行至少一个操作来提供改进的速度， 在相同时钟周期的第二个状态。 内容可寻址存储器（CAM）架构包括连接到比较数据写入驱动器和读/写块的CAM单元的阵列，用于接收比较数据并用于读取和/或写入数组中的数据 CAM单元，所述CAM单元的输出耦合到提供匹配输出信号线的匹配块，所述匹配输出信号线在搜索操作结束时识别匹配/不匹配;以及控制逻辑，用于在第一时间段期间实现搜索和地址解码操作 状态并且在匹配的情况下在相同时钟周期的第二状态内启用读或写操作。

公开(公告)号：US20040104750A1

公开(公告)日：2004-06-03

申请号：US10639248

申请日：2003-08-12

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajesh Bajaj ,  Nipun Padha

IPC: H03L007/06

CPC classification number: H03L7/18 ,  G06F1/10

Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree.

Abstract translation: 用于数字集成电路的改进的锁相环（PLL）。 该PLL的一个特点是通过时钟树副本将压控振荡器（VCO）输出馈送到相位和频率检测器（PFD）输入，提供等于路由时钟树的延迟。

公开(公告)号：US20030234667A1

公开(公告)日：2003-12-25

申请号：US10460040

申请日：2003-06-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kailash Digari ,  Nitin Deshmukh

IPC: G06F007/38

CPC classification number: H03K19/17772 ,  H03K19/1737 ,  H03K19/17728

Abstract: The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.

Abstract translation: 本发明提供了一种结合了双输入多路复用器的可编程逻辑器件（PLD），用于提供级联逻辑输出并具有耦合到选择线的级联逻辑输入。 双输入多路复用器提供所需的可配置级联逻辑功能，初始化电路在初始化配置位的控制下设置级联逻辑的初始值。 提供级联逻辑输出的多路复用器还使用查找表（LUT）和配置位提供所需的可配置级联逻辑功能。

公开(公告)号：US20030223298A1

公开(公告)日：2003-12-04

申请号：US10377297

申请日：2003-02-28

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Ankur Bal ,  Manish Agarwal

IPC: G11C007/00

CPC classification number: H03K19/17776 ,  G11C7/20 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

Abstract: An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device comprising a group of one or more data latches, each comprising a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose.

Abstract translation: 一种用于在包括FPGA的电子设备中初始化锁存器阵列的有效方法和电子电路，以及包括一组一个或多个数据锁存器的存储器件，每个数据锁存器包括一对交叉耦合的反相逻辑元件，其特征在于， 用于同时将每个数据锁存器初始化为预定的逻辑状态，而不需要任何额外的电路元件与任何数据锁存器用于此目的。

公开(公告)号：US20030218480A1

公开(公告)日：2003-11-27

申请号：US10407801

申请日：2003-04-04

Applicant: Indian ST (STMicroelectronics Pvt. Ltd.)

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/1774 ,  H03K19/17784

Abstract: An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Abstract translation: 一种包含一个或多个数字同步顺序逻辑块的电子电路，其中至少一个在操作期间被选择或取消选择。 电子电路包括一种降低功耗的改进的时钟分配方案，包括识别装置，用于确定每个所述可取消同步顺序逻辑块的选择/取消选择状态，耦合到禁用装置，用于禁止每个取消选择的同步顺序逻辑块的时钟输入。