公开(公告)号：US06628539B2

公开(公告)日：2003-09-30

申请号：US09872975

申请日：2001-05-31

Applicant: Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

Inventor： Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

IPC: G11C1900

CPC classification number: G11C11/419 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30141

Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

公开(公告)号：US06369616B1

公开(公告)日：2002-04-09

申请号：US09599050

申请日：2000-06-21

Applicant: Jiann-Cherng James Lan ,  Sudarshan Kumar

Inventor： Jiann-Cherng James Lan ,  Sudarshan Kumar

IPC: H03K19096

CPC classification number: H03K19/1731

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.

Abstract translation: 第一上拉晶体管具有耦合到时钟信号线的栅极和耦合到第一下拉晶体管和电压钳两者的漏极。 第二上拉晶体管具有还耦合到时钟信号线的栅极和耦合到第二下拉晶体管和电压钳两者的漏极。 共享上拉晶体管具有也耦合到时钟信号线的栅极和耦合到第一和第二下拉晶体管的漏极。 共享上拉晶体管可以用于对电路的输出节点进行预充电。 该电路可用于时钟缓冲应用。

公开(公告)号：US06351151B2

公开(公告)日：2002-02-26

申请号：US09909104

申请日：2001-07-18

Applicant: Sudarshan Kumar ,  Wenjie Jiang

Inventor： Sudarshan Kumar ,  Wenjie Jiang

IPC: H03K19096

CPC classification number: H03K19/00338 ,  H03K19/096

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract translation: 一种降低动态电路软错误的技术。 对于一个实施例，动态电路包括具有输出节点的动态逻辑门，在该输出节点检测逻辑门的逻辑输出值。 耦合到输出节点的保持器电路被配置为通过增加输出节点处的临界电荷来硬化动态电路。

公开(公告)号：US5944777A

公开(公告)日：1999-08-31

申请号：US851527

申请日：1997-05-05

Applicant: Sanjay Kumar ,  Sudarshan Kumar

Inventor： Sanjay Kumar ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/508

CPC classification number: G06F7/508

Abstract: An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.

Abstract translation: 用于产生进位的加法器电路和由加法器电路实现的方法。 计算第一组和第二组连续组生成项。 将组的第一组生成术语组合以计算第一逻辑电平的第一结果，并且组合第二组组生成术语以在相同逻辑电平处计算第二结果。 然后组合第一和第二结果以在第二逻辑电平计算进位输出。

公开(公告)号：US5900744A

公开(公告)日：1999-05-04

申请号：US774431

申请日：1996-12-30

Applicant: Bharat K. Bisen ,  Sudarshan Kumar

Inventor： Bharat K. Bisen ,  Sudarshan Kumar

IPC: H03K19/094 ,  H03K19/02 ,  H03K19/096

CPC classification number: H03K19/09429

Abstract: A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.

Abstract translation: 一种用于提供高速三态缓冲器的方法和装置。 该缓冲器包括一个p沟道上拉晶体管和一个传输门。 晶体管的源极耦合到电压源。 晶体管的漏极耦合到缓冲器输出端。 传输门的栅极耦合到第一时钟源。 传输门的输入是第二个时钟源，传输门的输出耦合到p沟道晶体管的栅极。

公开(公告)号：US5889693A

公开(公告)日：1999-03-30

申请号：US851220

申请日：1997-05-05

Applicant: Vivek Joshi ,  Sudarshan Kumar

Inventor： Vivek Joshi ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/505 ,  G06K7/50

CPC classification number: G06F7/5055 ,  G06F7/507

Abstract: A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.

Abstract translation: 提供了一种CMOS反相器的方法和装置，用于将第一数量增加一个，三个或两个倍数。 递增单元包括用于从第一数量提取多个最低有效位的提取/恢复单元，从而产生第二数量。 提取的最低有效位的数量由递增值确定。 增量单元还包括调整单元，用于将调整值与从第一数量提取的最低有效位相加，从而产生经调整的最低有效位。 递增单元还包括用于接收第二数量并递增第二数量的增量块，从而产生第四数。 所述提取/还原单元还用于将经调整的最低有效位恢复到第四数，从而产生最终结果。

公开(公告)号：US20120057135A1

公开(公告)日：2012-03-08

申请号：US12801468

申请日：2010-09-07

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G03B21/14

CPC classification number: H04N9/3111

Abstract: A system comprising of low cost and low power projection engine comprising of means of producing non-coherent light source, means of condensing non-coherent light into narrow beams, means of focusing and scanning narrow beam light on screen where as image is projected on screen by producing light for each pixel of image. Source of non-coherent light can be LED.

Abstract translation: 一种包括低成本和低功率投影引擎的系统，包括产生非相干光源的装置，将非相干光聚焦成窄光束的装置，在屏幕上聚焦和扫描窄光束的装置，其中图像被投影在屏幕上 通过为图像的每个像素产生光。 非相干光源可以是LED。

公开(公告)号：US06593776B2

公开(公告)日：2003-07-15

申请号：US09922434

申请日：2001-08-03

Applicant: Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

Inventor： Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

IPC: H03K1994

CPC classification number: G11C8/10

Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

Abstract translation: 解码器包括多个解码门，每个解码门提供解码输出信号的一位。 至少两个解码门共享晶体管。 根据一个方面，多个解码门中的每一个是偏斜门。

公开(公告)号：US6111435A

公开(公告)日：2000-08-29

申请号：US343961

申请日：1999-06-30

Applicant: Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

Inventor： Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

IPC: H03K17/693 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K17/693 ,  H03K19/1731

Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

Abstract translation: 电路包括第一和第二上拉晶体管，其分别具有分别耦合到单独的电压钳位的第一和第二漏极。 两个上拉晶体管中的每一个的栅极耦合到时钟信号线。 电路还包括共享下拉晶体管，其栅极耦合到时钟信号线。 共享下拉晶体管的漏极经由与共用下拉晶体管串联的至少一个下拉晶体管耦合到第一漏极。 共享下拉晶体管的漏极还通过与共享下拉晶体管串联的至少一个下拉晶体管耦合到第二漏极。 该电路可用于多路复用应用。

公开(公告)号：US6058403A

公开(公告)日：2000-05-02

申请号：US130379

申请日：1998-08-06

Applicant: Narsing K. Vijayrao ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Sudarshan Kumar

IPC: H03K19/096 ,  G06F7/74 ,  G06F7/00

CPC classification number: G06F7/74

Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.

Abstract translation: 一种破碎的堆叠多米诺骨牌优先编码器，用于提供一组电压以唯一地识别二进制字中的前导或前导零的位置，多米诺骨牌优先级编码器包括nMOSFET的旁路堆叠和破坏的nMOSFET堆叠，以排放各种 节点。 为了最大化优先编码器的切换速度，使每个节点和地之间的nMOSFET的堆叠深度最小化。