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    Using hardware checkpoints to support software based speculation
    13.
    发明申请
    Using hardware checkpoints to support software based speculation 审中-公开
    使用硬件检查点来支持基于软件的猜测

    公开(公告)号：US20080244544A1

    公开(公告)日：2008-10-02

    申请号：US11729724

    申请日：2007-03-29

    Applicant: Naveen Neelakantam ,  Craig Zilles ,  Uma Srinivasan ,  Suresh Srinivas ,  Ravi Rajwar ,  Konrad Lai

    Inventor： Naveen Neelakantam ,  Craig Zilles ,  Uma Srinivasan ,  Suresh Srinivas ,  Ravi Rajwar ,  Konrad Lai

    IPC: G06F9/45

    CPC classification number: G06F8/443

    Abstract: Hardware checkpoints may be used to mark software-based speculation regions. An instruction may be provided at the beginning of a speculation region and at the end of the speculation region. If an exception occurs during the speculation region, a hardware rollback may be occurred. The hardware rollback rolls back to the instruction at the beginning of the speculation region. The hardware may take a checkpoint by taking a register snapshot and treating future memory updates as tentative. When the instruction marking the end of the speculation is reached, all the tentative memory updates are committed and the previously taken register snapshot is discarded.

    Abstract translation: 硬件检查点可用于标记基于软件的推测区域。 可以在投机区域的开始处和投机区域的末尾提供指令。 如果在推测区域发生异常，则可能会发生硬件回滚。 硬件回滚回滚到投机区域开头的指令。 硬件可以通过注册快照并将未来的内存更新视为暂时性来检查点。 当达到臆测结束的指示时，所有暂时的内存更新被提交，并且先前注册的注册快照被丢弃。

    INSTRUCTION AND LOGIC TO PERFORM DYNAMIC BINARY TRANSLATION
    15.
    发明申请
    INSTRUCTION AND LOGIC TO PERFORM DYNAMIC BINARY TRANSLATION 有权
    指令和逻辑执行动态二进制翻译

    公开(公告)号：US20130283249A1

    公开(公告)日：2013-10-24

    申请号：US13995400

    申请日：2011-09-30

    Applicant: Abhay S. Kanhere ,  Paul Caprioli ,  Koichi Yamada ,  Suriya Madras-Subramanian ,  Suresh Srinivas

    Inventor： Abhay S. Kanhere ,  Paul Caprioli ,  Koichi Yamada ,  Suriya Madras-Subramanian ,  Suresh Srinivas

    IPC: G06F9/45

    CPC classification number: G06F8/40 ,  G06F8/456 ,  G06F8/51 ,  G06F9/30109 ,  G06F9/30185 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/4552

    Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.

    Abstract translation: 微架构可以提供硬件和软件协同设计的动态二进制翻译。 微架构可以调用执行动态二进制转换的方法。 该方法可以包括执行针对第一指令集编译的原始软件代码，使用处理器硬件来检测软件代码中的热点并将控制传递给二进制翻译翻译器，确定用于翻译的热点区域，使用 第二指令集，将转换的代码放置在转换高速缓存中，从翻译的高速缓存中执行转换的代码，并且在转换的代码完成执行之后转换回原始软件代码。

    PROFILE-BASED HARDWARE PREFETCHING
    16.
    发明申请
    PROFILE-BASED HARDWARE PREFETCHING 审中-公开
    基于配置文件的硬件预选

    公开(公告)号：US20130262779A1

    公开(公告)日：2013-10-03

    申请号：US13436790

    申请日：2012-03-30

    Applicant: Jayaram BOBBA ,  Ryan CARLSON ,  Jeffrey Cook ,  Abhinav DAS ,  Jason HORIHAN ,  Wei LI ,  Suresh SRINIVAS ,  Sreenivas SUBRAMONEY ,  Krishnaswamy VISWANATHAN

    Inventor： Jayaram BOBBA ,  Ryan CARLSON ,  Jeffrey Cook ,  Abhinav DAS ,  Jason HORIHAN ,  Wei LI ,  Suresh SRINIVAS ,  Sreenivas SUBRAMONEY ,  Krishnaswamy VISWANATHAN

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0862 ,  G06F2212/452 ,  G06F2212/6026

    Abstract: Profiling and analyzing modules may be combined with hardware modules to identify a likelihood that a particular region of code in a computer program contains data that would benefit from prefetching. Those regions of code that would not benefit from prefetching may also be identified. Once a region of code has been identified, a hardware prefetcher may be selectively enabled or disable when executing code in identified code region. In some instances, once a processing device finishes executing code in the identified code region, the state of the hardware prefetcher may then be switched back to its original state. Systems, methods, and media are provided.

    Abstract translation: 分析和分析模块可以与硬件模块组合，以识别计算机程序中特定的代码区域包含可从预取中受益的数据的可能性。 也可以识别那些不能从预取中获益的代码区域。 一旦已经识别出代码区域，则当在识别的代码区域中执行代码时，可以选择性地启用或禁用硬件预取器。 在一些情况下，一旦处理设备完成在所识别的代码区域中的执行代码，则硬件预取器的状态然后可以被切换回其原始状态。 提供系统，方法和媒体。

    Transitioning From Source Instruction Set Architecture (ISA) Code To Translated Code In A Partial Emulation Environment
    17.
    发明申请
    Transitioning From Source Instruction Set Architecture (ISA) Code To Translated Code In A Partial Emulation Environment 有权
    从源指令集体系结构（ISA）代码转换为部分仿真环境中的翻译代码

    公开(公告)号：US20110153307A1

    公开(公告)日：2011-06-23

    申请号：US12646054

    申请日：2009-12-23

    Applicant: Sebastian Winkel ,  Koichi Yamada ,  Suresh Srinivas ,  James E. Smith

    Inventor： Sebastian Winkel ,  Koichi Yamada ,  Suresh Srinivas ,  James E. Smith

    IPC: G06F9/30 ,  G06F12/08 ,  G06F9/455 ,  G06F12/00

    CPC classification number: G06F9/3017 ,  G06F9/455 ,  G06F12/0873 ,  G06F12/0875

    Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器可以在多种模式下操作，包括直接执行模式和仿真执行模式。 更具体地，处理器可以在部分仿真模型中操作，其中以直接执行模式直接处理源指令集架构（ISA）指令，并且在仿真执行模式中处理由仿真引擎生成的转换代码。 实施例还可以使用可以存储在处理器的一个或多个存储器和系统中的其他地方的信息来提供模式之间的有效转换。 描述和要求保护其他实施例。

    Method and apparatus for hardware-based dynamic escape detection in managed run-time environments
    20.
    发明申请
    Method and apparatus for hardware-based dynamic escape detection in managed run-time environments 审中-公开
    在管理的运行时环境中用于基于硬件的动态逃逸检测的方法和装置

    公开(公告)号：US20070162475A1

    公开(公告)日：2007-07-12

    申请号：US11322484

    申请日：2005-12-30

    Applicant: Quinn Jacobson ,  Suresh Srinivas ,  Anne Bracy ,  Hong Wang

    Inventor： Quinn Jacobson ,  Suresh Srinivas ,  Anne Bracy ,  Hong Wang

    IPC: G06F7/00

    CPC classification number: G06F12/0802 ,  G06F12/0269

    Abstract: A method and apparatus for hardware-based dynamic escape detection in managed run-time environments are described. In one embodiment, the method includes the detection of a pointer update of a first object having a global scope. In one embodiment, a single instruction is issued to assert that a scope attribute associated with a target object of the pointer update identifies a global scope. The single instruction may return failure if the scope attribute that is associated with the second object identifies the scope of the second object as local. Verification may include the reading of an object descriptor for the second object to determine whether a scope attribute of the object descriptor indicates that the scope of the second object is local. Once verified, in one embodiment, the second object, and each object reachable from the second object, are converted into global objects. Other embodiments are described and claimed.

    Abstract translation: 描述了在受管运行时环境中用于基于硬件的动态逃逸检测的方法和装置。 在一个实施例中，该方法包括检测具有全局范围的第一对象的指针更新。 在一个实施例中，发出单个指令以断言与指针更新的目标对象相关联的范围属性标识全局范围。 如果与第二个对象相关联的范围属性将第二个对象的范围标识为本地，单个指令可能会返回失败。 验证可以包括读取第二对象的对象描述符，以确定对象描述符的范围属性是否指示第二对象的范围是本地的。 一旦验证，在一个实施例中，第二对象和从第二对象可访问的每个对象被转换成全局对象。 描述和要求保护其他实施例。

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