公开(公告)号：US08354706B2

公开(公告)日：2013-01-15

申请号：US12719193

申请日：2010-03-08

申请人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

摘要翻译： 根据本发明实施例的半导体存储器件包括衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅绝缘体上的第一浮栅，第二栅绝缘体 形成在第一浮栅上并用作FN隧穿膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极 所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

公开(公告)号：US08289782B2

公开(公告)日：2012-10-16

申请号：US12719420

申请日：2010-03-08

申请人： Takashi Izumida ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： G11C16/04

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the first intergate insulator, a second intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the second intergate insulator.

摘要翻译： 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的栅极绝缘体，形成在栅极绝缘体上的第一浮栅，第一栅极绝缘体 形成在第一浮栅上并用作FN隧道膜，形成在第一栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的第二栅极绝缘体，以及形成在第一浮栅上的控制栅 第二隔间绝缘子。

公开(公告)号：US08134203B2

公开(公告)日：2012-03-13

申请号：US12618119

申请日：2009-11-13

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/788 ,  H01L29/423

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。

公开(公告)号：US07989856B2

公开(公告)日：2011-08-02

申请号：US12335701

申请日：2008-12-16

申请人： Masakazu Goto ,  Nobutoshi Aoki ,  Takashi Izumida ,  Kimitoshi Okano ,  Satoshi Inaba ,  Ichiro Mizushima

发明人： Masakazu Goto ,  Nobutoshi Aoki ,  Takashi Izumida ,  Kimitoshi Okano ,  Satoshi Inaba ,  Ichiro Mizushima

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/7845

摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

摘要翻译： 翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。

公开(公告)号：US20080251854A1

公开(公告)日：2008-10-16

申请号：US12100621

申请日：2008-04-10

申请人： Yoshiaki SHIMOOKA ,  Takashi IZUMIDA ,  Hiroki OKAMOTO

发明人： Yoshiaki SHIMOOKA ,  Takashi IZUMIDA ,  Hiroki OKAMOTO

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L27/092 ,  H01L29/7843 ,  H01L29/7846

摘要： In one aspect of the present invention, semiconductor device, may include a p-channel semiconductor active region, an n-channel semiconductor active region, an element isolation insulating layer which electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region, and an insulating layer made of a material different from that of the element isolation insulating layer, and being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region to apply a compression stress in the channel length direction to a channel of the p-channel semiconductor active region, wherein the p-channel semiconductor active region is surrounded by the insulating layer, which is in contact with the both ends, in the channel length direction, of the p-channel semiconductor active region, and the p-channel semiconductor active region is surrounded by the element isolation insulating layer, which is in contact with the side surfaces, approximately parallel to the channel length direction, of the p-channel semiconductor active region, and the n-channel semiconductor active region is surrounded by the element isolation insulating layer.

摘要翻译： 在本发明的一个方面，半导体器件可以包括p沟道半导体有源区，n沟道半导体有源区，将p沟道半导体有源区与n沟道半导体电隔离的元件隔离绝缘层 有源区，以及由与元件隔离绝缘层不同的材料制成的绝缘层，并且在其沟道长度方向上与p沟道半导体有源区的两端接触，以在该沟道长度方向上施加压缩应力 沟道长度方向到p沟道半导体有源区的沟道，其中p沟道半导体有源区被p沟道的沟道长度方向上与两端接触的绝缘层包围 半导体有源区和p沟道半导体有源区被与侧面接触的元件隔离绝缘层包围 大致平行于沟道长度方向的表面，并且n沟道半导体有源区被元件隔离绝缘层包围。

公开(公告)号：US20080179659A1

公开(公告)日：2008-07-31

申请号：US12021003

申请日：2008-01-28

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Takashi Izumida

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Takashi Izumida

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.

摘要翻译： 关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一 选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极 形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

公开(公告)号：US20070210355A1

公开(公告)日：2007-09-13

申请号：US11713803

申请日：2007-03-05

申请人： Takashi Izumida

发明人： Takashi Izumida

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/6659 ,  H01L29/7843

摘要： A semiconductor device includes: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed at least to a side face of the channel section in the semiconductor fin and extending in a second direction that is substantially orthogonal to the first direction and parallel to the major surface of the insulating layer; an insulating film interposed between the semiconductor fin and the gate electrode; a spacer layer provided on the channel section; a sidewall insulating layer provided adjacent to a side face of the spacer layer substantially parallel to the second direction; and a stress liner. The stress liner covers the sidewall insulating layer and the spacer layer and has an intrinsic stress for distorting the semiconductor fin. The sidewall insulating layer has a thickness of 45 nanometers (nm) or more in the first direction, and the spacer layer has a height of 105 nanometers (nm) or more.

摘要翻译： 半导体器件包括：绝缘层; 从所述绝缘层突出的半导体鳍片，沿着与所述绝缘层的主表面平行的第一方向延伸，并且具有沿所述第一方向排列的源极区域，沟道部分和漏极区域; 至少与所述半导体鳍片中的沟道部分的侧面相对且在与所述第一方向大致正交且平行于所述绝缘层的主表面的第二方向上延伸的栅电极; 介于所述半导体鳍片和所述栅电极之间的绝缘膜; 间隔层，设置在通道部分上; 侧壁绝缘层，设置成与所述间隔层的与所述第二方向大致平行的侧面相邻; 和应力衬垫。 应力衬垫覆盖侧壁绝缘层和间隔层，并且具有使半导体翅片变形的固有应力。 侧壁绝缘层在第一方向上具有45纳米（nm）以上的厚度，间隔层的高度为105纳米（nm）以上。

公开(公告)号：US20070170509A1

公开(公告)日：2007-07-26

申请号：US11401928

申请日：2006-04-12

申请人： Takashi Izumida

发明人： Takashi Izumida

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of the Fin. The first extension region is formed between the source region and the drain region within the Fin in contact with the source region. The second extension region is formed between the source region and the drain region within the Fin in contact with the drain region. The channel region is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region.

摘要翻译： 半导体器件包括Fin，源极区和漏极区，第一延伸区，第二延伸区和沟道区。 鳍形成在半导体衬底的主表面上。 源极区域和漏极区域形成在鳍片的两个端部处。 第一延伸区形成在与源极区域接触的鳍内的源极区域和漏极区域之间。 第二延伸区域形成在与漏极区域接触的鳍内的源极区域和漏极区域之间。 沟道区域位于鳍内的第一延伸区域和第二延伸区域之间，沟道区域的鳍的高度大于第一延伸区域和第二延伸区域中的每一个的鳍的高度。

公开(公告)号：US07115476B1

公开(公告)日：2006-10-03

申请号：US11201264

申请日：2005-08-11

申请人： Takashi Izumida

发明人： Takashi Izumida

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66772 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a semiconductor pillar, doping an impurity into the semiconductor substrate, thereby forming a first source/drain region in part of the semiconductor substrate, which is located under the semiconductor pillar, forming a gate insulating film on the semiconductor substrate, which contacts a side surface of the semiconductor pillar, forming a gate electrode on a side surface of the gate insulating film, forming a first insulating layer on the gate electrode, which contacts a side surface of the semiconductor pillar, and doping the impurity into the first insulating layer, thereby forming a second source/drain region in part of the semiconductor pillar, which is located on a side surface of the first insulating layer.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成半导体柱，将杂质掺杂到半导体衬底中，从而形成第一源极/漏极 位于所述半导体柱下方的半导体衬底的一部分中，在所述半导体衬底上形成与所述半导体柱的侧面接触的栅极绝缘膜，在所述栅极绝缘膜的侧面形成栅电极， 在所述栅电极上形成第一绝缘层，所述第一绝缘层与所述半导体柱的侧表面接触，并将所述杂质掺杂到所述第一绝缘层中，从而在半导体柱的一部分中形成第二源/漏区， 第一绝缘层的侧表面。

公开(公告)号：US08680612B2

公开(公告)日：2014-03-25

申请号：US13601400

申请日：2012-08-31

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

摘要： According to one embodiment, a semiconductor device includes an element region partitioned by an isolation region in a semiconductor substrate, and a source region and a drain region formed in a surface layer of the element region by being isolated by a gate trench along a predetermined direction across the element region. The semiconductor device includes a gate electrode formed to reach a position deeper than the source region and the drain region by embedding at least part thereof in the gate trench with a gate dielectric film interposed therebetween. An interface in the drain region, which is in contact with the gate dielectric film, includes a projection projecting toward the gate electrode side.

摘要翻译： 根据一个实施例，半导体器件包括由半导体衬底中的隔离区分隔开的元件区域，以及通过沿预定方向的栅极沟槽隔离形成在元件区域的表面层中的源极区域和漏极区域 跨越元素区域。 半导体器件包括通过在栅极沟槽中至少部分地嵌入栅极电介质膜而形成为达到比源极区域和漏极区域更深的位置的栅电极。 与栅极电介质膜接触的漏极区域中的界面包括向栅电极侧突出的突起。