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11.发明申请Mechanism for Detecting Human Presence Using Authenticated Input Activity Timestamps 审中-公开使用认证输入活动时间戳检测人类存在的机制公开(公告)号：US20140115662A1
公开(公告)日：2014-04-24
申请号：US14144757
申请日：2013-12-31
Applicant: Erik J. Johnson , Jasmeet Chhabra , Steve Orrin , Travis T. Schluessler , Stephen D. Goglin
Inventor： Erik J. Johnson , Jasmeet Chhabra , Steve Orrin , Travis T. Schluessler , Stephen D. Goglin
IPC: G06F21/30
CPC classification number: G06F21/30 , G06F21/316 , G06F2221/2151
Abstract: When a service request associated with an initiated online service transaction is received, an attestation identifying a human-input activity is requested. Upon receiving a signature attesting the human-input activity, the previously initiated service transaction is authenticated based at least in part on the signature.
Abstract translation: 当接收到与启动的在线服务事务相关联的服务请求时，请求识别人员输入活动的证明。 在接收到证明人类输入活动的签名之后，至少部分地基于签名验证先前发起的服务事务。
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12.发明申请公开(公告)号：US20130159741A1
公开(公告)日：2013-06-20
申请号：US13398641
申请日：2012-02-16
Applicant: Travis T. Schluessler , Russell J. Fenger
Inventor： Travis T. Schluessler , Russell J. Fenger
CPC classification number: G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
Abstract translation: 这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。 如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。 然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。 因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。
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13.发明申请METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING POWER AND PERFORMANCE BALANCING BETWEEN MULTIPLE PROCESSING ELEMENTS 有权能源效率和能源保护的方法，装置和系统，包括多个处理元件之间的功率和性能平衡公开(公告)号：US20120324248A1
公开(公告)日：2012-12-20
申请号：US13327670
申请日：2011-12-15
Applicant: Travis T. Schluessler , Russell J. Fenger
Inventor： Travis T. Schluessler , Russell J. Fenger
IPC: G06F1/26
CPC classification number: G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
Abstract translation: 这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。 如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。 然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。 因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。
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公开(公告)号：US20120102285A1
公开(公告)日：2012-04-26
申请号：US13336913
申请日：2011-12-23
Applicant: Uday Savagaonkar , Travis T. Schluessler , Hormuzd Khosravi , Ravi Sahita , Gayathri Nagabhushan , David Durham
Inventor： Uday Savagaonkar , Travis T. Schluessler , Hormuzd Khosravi , Ravi Sahita , Gayathri Nagabhushan , David Durham
IPC: G06F12/14
CPC classification number: G06F12/145
Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing hardware of a virtualized processor based system detecting a specified type of memory access to an identified region of memory and in response to the detecting generating an interrupt for a virtual machine monitor (VMM) of the virtualized processor based system.
Abstract translation: 根据所公开的实施例，提供了用于实现基于虚拟处理器的系统的硬件的方法，系统和装置，该系统检测对所识别的存储器区域的指定类型的存储器访问，并且响应于该检测产生虚拟机的中断 基于虚拟化处理器的系统的监视器（VMM）。
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15.发明授权Methods and apparatus for providing an insertion and integrity protection system associated with a wireless communication platform 有权用于提供与无线通信平台相关联的插入和完整性保护系统的方法和装置公开(公告)号：US07921463B2
公开(公告)日：2011-04-05
申请号：US11239976
申请日：2005-09-30
Applicant: Kapil Sood , Travis T. Schluessler , Christopher Lord
Inventor： Kapil Sood , Travis T. Schluessler , Christopher Lord
CPC classification number: H04L63/123 , H04L63/04 , H04L63/1441 , H04W12/02 , H04W12/10 , H04W12/12
Abstract: Embodiments of methods and apparatus for providing an insertion and integrity protection system associated with a wireless communication platform are generally described herein. Other embodiments may be described and claimed.
Abstract translation: 这里通常描述用于提供与无线通信平台相关联的插入和完整性保护系统的方法和装置的实施例。 可以描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US07739517B2
公开(公告)日：2010-06-15
申请号：US11096591
申请日：2005-03-31
Applicant: Ravi Sahita , Travis T. Schluessler , David M. Durham , Amir Zinaty
Inventor： Ravi Sahita , Travis T. Schluessler , David M. Durham , Amir Zinaty
IPC: H04L9/00
CPC classification number: G06F12/1458 , G06F21/31 , G06F21/57 , G06F2221/2153
Abstract: Identity of software is authenticated with hardware on a system. The hardware may be accessible to the operating system, making the mechanisms available to software makers. The identity of the software may be authenticated using fundamental properties of the software itself, providing greater security than merely relying on transferable identifiers, for example, keys.
Abstract translation: 软件的身份由系统上的硬件进行身份验证。 操作系统可以访问硬件，使得软件制造商可以使用这些机制。 可以使用软件本身的基本属性来认证软件的身份，提供比仅依靠可转移标识符（例如密钥）更大的安全性。
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公开(公告)号：US20100131781A1
公开(公告)日：2010-05-27
申请号：US12313548
申请日：2008-11-21
Applicant: Mazhar I. Memon , Steen K. Larsen , Bryan E. Veal , Daniel S. Lake , Travis T. Schluessler
Inventor： Mazhar I. Memon , Steen K. Larsen , Bryan E. Veal , Daniel S. Lake , Travis T. Schluessler
Abstract: In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于在分组缓冲器中接收输入分组并将其与流标识符相关联的方法。 基于流标识符，可以确定输入分组将被引导到的核心，并且可以发送功率管理提示以使得核心被加电。 描述和要求保护其他实施例。
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公开(公告)号：US20090144825A1
公开(公告)日：2009-06-04
申请号：US11998822
申请日：2007-11-30
Applicant: Travis T. Schluessler , Stephen D. Goglin , Erik J. Johnson
Inventor： Travis T. Schluessler , Stephen D. Goglin , Erik J. Johnson
IPC: G08B23/00
CPC classification number: G06F21/57 , G06F21/53 , G06F21/552 , G06F21/554 , G06F2221/2109
Abstract: In general, in one aspect, an interface chipset includes at least one interface to receive user commands from input devices, filters to monitor the received user commands and to copy the user commands associated with at least a subset of the input devices, and an isolated execution environment. The isolated execution environment is to provide a secure communication link between an on-line application and a remote service provider. The isolated execution environment is also to detect at least some subset of user command modifications, on-line application code modifications, and on-line application process flow modifications. The isolated execution environment is further to notify the remote service provider when a modification is detected via the secure communication link.
Abstract translation: 通常，在一个方面，接口芯片组包括至少一个接口，用于接收来自输入设备的用户命令，监视所接收的用户命令的过滤器以及复制与至少一个输入设备子集相关联的用户命令，以及隔离的 执行环境。 隔离的执行环境是在在线应用和远程服务提供商之间提供安全的通信链路。 隔离的执行环境还用于检测用户命令修改，在线应用程序代码修改和在线应用程序流程修改的至少一些子集。 隔离的执行环境进一步通过安全通信链路检测到修改时通知远程服务提供商。
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公开(公告)号：US20180300840A1
公开(公告)日：2018-10-18
申请号：US15488632
申请日：2017-04-17
Applicant: Joydeep Ray , Prasoonkumar Surti , Abhishek R. Appu , Travis T. Schluessler , Linda L. Hurd , Eric J. Hoekstra
Inventor： Joydeep Ray , Prasoonkumar Surti , Abhishek R. Appu , Travis T. Schluessler , Linda L. Hurd , Eric J. Hoekstra
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to render data from an application to be displayed on a display panel, and a memory to store the compressed final display surface writes. The processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display.
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公开(公告)号：US20180300238A1
公开(公告)日：2018-10-18
申请号：US15488637
申请日：2017-04-17
Applicant: Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
Inventor： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC: G06F12/06
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.
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