公开(公告)号：US06459733B1

公开(公告)日：2002-10-01

申请号：US09372490

申请日：1999-08-12

申请人： Yutaka Yokoyama ,  Yasushi Ooi

发明人： Yutaka Yokoyama ,  Yasushi Ooi

IPC分类号： H04N712

CPC分类号： H04N19/85 ,  H04N19/105 ,  H04N19/115 ,  H04N19/124 ,  H04N19/142 ,  H04N19/149 ,  H04N19/172 ,  H04N19/179 ,  H04N19/182 ,  H04N19/61

摘要： Video images including a fade transition are encoded using inter-frame prediction. A fade detector is provided to detect a fade transition by way of analyzing incoming images successively applied thereto. The fade detector generates first information indicating if the fade transition is fade-in fade-out, and also predicts fade duration and then generates second information indicating the predicted fade duration. A bit amount adjuster is provided to adjust allocated bit amount during fade using the first and second information. A motion image encoder is provided to encode the incoming images using the number of bits which has been determined by the bit amount adjuster.

摘要翻译： 使用帧间预测编码包括淡入变换的视频图像。 提供了一种渐变检测器，用于通过分析连续施加到其上的输入图像来检测淡入变换。 衰落检测器产生指示淡入淡出淡入淡出的第一信息，并且还预测衰落持续时间，然后产生指示预测的衰落持续时间的第二信息。 提供位量调节器以在使用第一和第二信息的渐变期间调整分配的位量。 提供运动图像编码器以使用由位量调节器确定的位数来对输入图像进行编码。

公开(公告)号：US5579498A

公开(公告)日：1996-11-26

申请号：US617427

申请日：1996-03-18

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F17/10

CPC分类号： G06F9/3873 ,  G06F17/10 ,  G06F9/30079 ,  G06F9/3867

摘要： A pipelined data processing system has an instruction set containing a stall instruction, and includes a plurality of stages and a pipeline controller for controlling execution and stall of a pipeline operation. The pipeline controller is configured to put the stages into a "frozen" condition on the basis of a stall signal generated by execution of the stall instruction, and to return the stages from the "frozen" condition to a "run" condition on the basis of an output pulse generated by a timer designated by an operand part of the stall instruction.

摘要翻译： 流水线数据处理系统具有包含停止指令的指令集，并且包括多个级和用于控制流水线操作的执行和停止的流水线控制器。 流水线控制器被配置为基于通过执行失速指令而产生的失速信号将各级置于“冻结”状态，并且将阶段从“冻结”状态返回到“运行”状态 由由停止指令的操作数部分指定的定时器产生的输出脉冲。

公开(公告)号：US5555511A

公开(公告)日：1996-09-10

申请号：US330550

申请日：1994-10-28

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04N19/60 ,  G06F17/16 ,  G06T9/00 ,  H03M7/30 ,  H04N1/41 ,  H04N19/423 ,  H04N19/48 ,  H04N19/625 ,  H04N19/91 ,  H04J3/22

CPC分类号： G06T9/005 ,  G06T9/007

摘要： A data processing system for a picture coding, includes a data memory for storing a discrete cosine transform (DCT) coefficient data successively transferred one after another, a flipflop set prior to the successive transfer of the DCT coefficient data, and a non-zero detector for detecting a non-zero data when the DCT coefficient data is successively transferred. When the non-zero data is detected, the non-zero detector resets the flipflop. When the successive transfer of the DCT coefficient data has been completed, an entropy coding central processing unit (CPU) discriminates on the basis of the condition of the flipflop whether or not all of the data stored in the data memory is zero, so that if the condition of the flipflop indicates that all of the data stored in the data memory is zero, the entropy coding CPU does not read the data memory.

摘要翻译： 一种用于图像编码的数据处理系统，包括数据存储器，用于存储一个接一个地连续传送的离散余弦变换（DCT）系数数据，在连续传送DCT系数数据之前的触发器组，以及非零检测器 用于当连续传送DCT系数数据时检测非零数据。 当检测到非零数据时，非零检测器复位触发器。 当DCT系数数据的连续传送已经完成时，熵编码中央处理单元（CPU）将根据触发器的状况来识别存储在数据存储器中的所有数据是否为零，从而如果 触发器的条件指示存储在数据存储器中的所有数据为零，熵编码CPU不读取数据存储器。

公开(公告)号：US5043878A

公开(公告)日：1991-08-27

申请号：US393039

申请日：1989-08-09

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F9/30 ,  G06F9/46

CPC分类号： G06F9/52 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30079

摘要： A data processing apparatus has a plurality of execution status and is adapted to control in accordance with the respective execution conditions the allowance of the execution of an instruction requiring the reference to the internal resource. The processing apparatus also comprises a register for holding the execution status, and another register for holding information controlling the reference to the internal resource. A comparator responds to the contents of the first and second registers to output a signal indicating whether the reference is allowed or not. The output signal and a strobe signal are fed to a gate, which then controls an actual reference to the internal resource.

摘要翻译： 数据处理装置具有多个执行状态，并且适于根据各个执行条件来控制需要引用内部资源的指令的执行。 处理装置还包括用于保持执行状态的寄存器和用于保存控制对内部资源的引用的信息的另一个寄存器。 比较器响应第一和第二寄存器的内容，以输出指示是否允许引用的信号。 输出信号和选通信号被馈送到门，然后控制对内部资源的实际参考。

公开(公告)号：US08179956B2

公开(公告)日：2012-05-15

申请号：US12318642

申请日：2009-01-05

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H03H7/40 ,  G06F17/10

CPC分类号： H04L25/03057 ,  H04L2025/03681

摘要： An adaptive equalizer includes an adaptive filter and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal so as to make an amplitude of an equalized output signal constant, the input signal being modulated by a modulation system that produces a modulation signal with constant amplitude characteristics. The control unit gradually changes equalization ability of the adaptive equalization processing of the adaptive filter in accordance with characteristics of the input signal.

摘要翻译： 自适应均衡器包括自适应滤波器和控制单元。 自适应滤波器对输入信号执行自适应均衡处理，以使均衡输出信号的幅度恒定，输入信号由产生具有恒定幅度特性的调制信号的调制系统调制。 控制单元根据输入信号的特性逐渐改变自适应滤波器的自适应均衡处理的均衡能力。

公开(公告)号：US08019297B2

公开(公告)日：2011-09-13

申请号：US12314831

申请日：2008-12-17

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H03D7/16

CPC分类号： H03D3/008 ,  H03J1/005

摘要： A radio receiver includes a frequency converter, an oscillation circuit, an A/D converter, and a digital demodulator. The A/D converter digitally samples the intermediate frequency signal by using one of an oscillating frequency, a multiplying frequency, and a dividing frequency of the clock signal as a sampling frequency. The digital demodulator performs a digital demodulation processing by using the intermediate frequency signal digitally sampled and by using the one of the oscillating frequency, the multiplying frequency, and the dividing frequency of the clock signal as an operating frequency. The oscillating frequency is within a predetermined range. The predetermined range is at least one of equal to or more than 37.1 MHz and less than or equal to 37.9 MHz, equal to or more than 54.1 MHz and less than or equal to 64.8 MHz, and equal to or more than 74.2 MHz and less than or equal to 75.8 MHz.

摘要翻译： 无线电接收机包括频率转换器，振荡电路，A / D转换器和数字解调器。 A / D转换器通过使用振荡频率，乘法频率和时钟信号的除频率之一作为采样频率对中频信号进行数字采样。 数字解调器通过使用数字采样的中频信号和通过使用时钟信号的振荡频率，乘法频率和分频频率中的一个作为工作频率来执行数字解调处理。 振荡频率在预定范围内。 预定范围是等于或大于37.1MHz且小于或等于37.9MHz，等于或大于54.1MHz且小于或等于64.8MHz，等于或大于74.2MHz和更小的至少一个 大于或等于75.8MHz。

公开(公告)号：US06950465B1

公开(公告)日：2005-09-27

申请号：US09574411

申请日：2000-05-18

申请人： Yutaka Yokoyama ,  Yasushi Ooi

发明人： Yutaka Yokoyama ,  Yasushi Ooi

IPC分类号： H04N19/50 ,  H04N5/14 ,  H04N7/12 ,  H04N11/02 ,  H04N19/102 ,  H04N19/103 ,  H04N19/105 ,  H04N19/12 ,  H04N19/134 ,  H04N19/139 ,  H04N19/172 ,  H04N19/176 ,  H04N19/196 ,  H04N19/503 ,  H04N19/51 ,  H04N19/513 ,  H04N19/57 ,  H04N19/593 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91

CPC分类号： H04N5/145 ,  H04N19/114 ,  H04N19/137 ,  H04N19/139 ,  H04N19/159 ,  H04N19/172

摘要： In a video coding apparatus, coding/decoding circuitry provides motion-compensated inter-frame prediction coding on input frames by using reference frames so that the input frames are coded into an intra-frame coded picture, a predictive coded picture or a bi-directionally predictive coded picture and decoding the coded frames to produce reference frames. Decision circuitry determines the magnitude of motion of the input frames relative to the reference frames, determines the interval between successive frames of the predictive coded picture according to the determined magnitude of motion and reorders the input frames according to the determined interval.

摘要翻译： 在视频编码装置中，编码/解码电路通过使用参考帧对输入帧提供运动补偿帧间预测编码，使得输入帧被编码成帧内编码图像，预测编码图像或双向编码图像 预测编码图像和解码编码帧以产生参考帧。 决定电路确定输入帧相对于参考帧的运动幅度，根据确定的运动幅度确定预测编码图像的连续帧之间的间隔，并根据所确定的间隔重新排序输入帧。

公开(公告)号：US5398027A

公开(公告)日：1995-03-14

申请号：US101357

申请日：1993-08-03

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F5/00 ,  H03M7/42 ,  H03M7/40

CPC分类号： H03M7/425

摘要： A variable length code decoding circuit includes a decoding table storing data, which has an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding the variable bit length code per n bits (n is an integer greater than or equal to 2), an intermediate field indicative of a shifting magnitude of the shift register upon completion of decoding, and a lower field indicative of a state of code decoding. The bit sequence of the variable bit length code in a shift register is shifted in a magnitude corresponding to a shifting magnitude indicated in the intermediate field when data indicative of the code decoding state in the lower field of the data read out from the decoding table storage means indicates completion of decoding and corresponding to n bits when the data indicative of the code decoding state in the lower field indicates continuation of decoding. An address for accessing the decoding table is generated by replacing the intermediate field and the lower field with leading n bits of the shift register.

摘要翻译： 可变长度码解码电路包括存储数据的解码表，其具有选择性地指示代码的含义的上部字段和用于下一次访问的地址，其根据每n位解码可变位长度代码时的状态转换而选择（ n是大于或等于2的整数），指示在解码完成时移位寄存器的移位幅度的中间字段，以及表示代码解码状态的较低字段。 移位寄存器中的可变位长度代码的比特序列在对应于在中间字段中指示的移位幅度的量值中移位，当指示从解码表存储器读出的数据的下部字段中的代码解码状态 当表示下部字段中的代码解码状态的数据表示解码继续时，表示完成解码并对应于n位。 通过用移位寄存器的前导n位替换中间场和下位域来生成用于访问解码表的地址。

公开(公告)号：US4924376A

公开(公告)日：1990-05-08

申请号：US947209

申请日：1986-12-29

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3824

摘要： An instruction code access control system used in an instruction code prefetched computer system includes at least an instruction buffer for accumulating prefetched instruction codes, and a data path switch for selectively coupling the instruction buffer to a data path through which an instruction code and an operand data are selectively transferred. The system also comprises a fetch counter for counting the number of the instruction codes accumulated in the instruction buffer from the time a discontinuous program control is carried out. There is provided a counter detector for comparing the value of the fetch counter with a predetermined value. An arbiter is provided for determining, on the basis of the output of the counter detector, a priority between an instruction memory access for instruction code prefetching and an operand access caused as the result of an instruction execution. The arbiter operates to control the data path switch in accordance with the result of the determination.

摘要翻译： 在指令代码预取计算机系统中使用的指令代码访问控制系统至少包括用于累加预取指令代码的指令缓冲器，以及用于选择性地将指令缓冲器耦合到数据通路的数据通路开关，通过该指令代码和操作数据 被选择性转移。 该系统还包括一个提取计数器，用于从执行不连续的程序控制的时间开始对累加在指令缓冲器中的指令代码的数量进行计数。 提供了一种用于将提取计数器的值与预定值进行比较的计数器检测器。 提供了一种仲裁器，用于根据计数器检测器的输出确定用于指令代码预取的指令存储器存取和作为指令执行结果引起的操作数访问之间的优先级。 仲裁器操作以根据确定的结果控制数据路径切换。

公开(公告)号：US4833642A

公开(公告)日：1989-05-23

申请号：US176008

申请日：1988-03-31

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0864 ,  G06F2212/601

摘要： An associative type cache controller includes a plurality of directory banks each holding an address tag of a cache block, each of the directory banks having a comparison circuit for comparing the content of the directory bank with a tag portion of a current reference address. The cache controller comprises a register for holding the association unit number, and a replacement block determining unit for indicating, in accordance with the content of the association unit number holding register, the directory bank including the cache block to be replaced at the time of cache replacement, so that the replacement directory banks are limited in accordance with the designated association unit number. Thus, the association unit number of a related cache memory can be changeably designated.