公开(公告)号：US20130018934A1

公开(公告)日：2013-01-17

申请号：US13547212

申请日：2012-07-12

Applicant: Yong June Kim ,  Jung Soo Chung ,  Jun Jin Kong ,  Hongrak Son

Inventor： Yong June Kim ,  Jung Soo Chung ,  Jun Jin Kong ,  Hongrak Son

IPC: G06F7/58 ,  G06F12/00

CPC classification number: G06F7/582

Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

Abstract translation: 用于操作控制器的方法可以包括将从PN序列发生器提供的伪噪声（PN）序列存储在种子表的第i个区域中，并将PN序列从第i个区域循环移位到第（i + 1个） ）表中的区域形成表。 该表可能包括行和列区域。 用于操作控制器的方法可以包括从序列发生器接收序列，将序列分解成种子单元，将分离序列存储在种子表的第j个区域中，以及形成包括与分离序列相对应的种子单元的表 存储在第j个区域。 用于操作控制器的方法可以包括将从序列生成器提供的序列存储在包括多个区域的种子表中，并且将表中的序列循环移位，直到在每个区域中形成种子。

公开(公告)号：US08347194B2

公开(公告)日：2013-01-01

申请号：US12428511

申请日：2009-04-23

Applicant: Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

Inventor： Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

IPC: G06F11/00

CPC classification number: H03M13/2906 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1194 ,  H03M13/136 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/296 ,  H03M13/3707 ,  H03M13/3738

Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.

Abstract translation: 解码器包括多个解码器级和控制器。 解码器级使用相应的不同解码算法对接收到的信号执行解码操作。 控制器确定解码器中的一个相对于接收信号执行的解码操作是否成功，并且响应于确定的结果来控制每个其他解码器级的解码操作。

公开(公告)号：US08274840B2

公开(公告)日：2012-09-25

申请号：US12498508

申请日：2009-07-07

Applicant: Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

Inventor： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

IPC: G11C11/34

CPC classification number: G11C16/16

Abstract: Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

Abstract translation: 非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

公开(公告)号：US20110038207A1

公开(公告)日：2011-02-17

申请号：US12856698

申请日：2010-08-16

Applicant: Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

Inventor： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642

Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

Abstract translation: 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

公开(公告)号：US20100296350A1

公开(公告)日：2010-11-25

申请号：US12774814

申请日：2010-05-06

Applicant: Yong June KIM ,  Jae Hong KIM ,  Jun Jin KONG ,  Hong Rak SON ,  Seung-Hwan SONG

Inventor： Yong June KIM ,  Jae Hong KIM ,  Jun Jin KONG ,  Hong Rak SON ,  Seung-Hwan SONG

IPC: G11C7/06

CPC classification number: G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

Abstract: A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.

Abstract translation: 一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。 在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

公开(公告)号：US20100251077A1

公开(公告)日：2010-09-30

申请号：US12729285

申请日：2010-03-23

Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC: G06F12/02 ,  H03M13/05 ,  G06F11/10

CPC classification number: G06F11/1048

Abstract: A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.

Abstract translation: 存储装置包括控制器单元和存储单元阵列。 控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。 存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。 第一存储器具有与第二存储器不同的存储单元结构。

公开(公告)号：US20100174959A1

公开(公告)日：2010-07-08

申请号：US12652768

申请日：2010-01-06

Applicant: Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

Inventor： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

IPC: H03M13/03 ,  G06F11/10

CPC classification number: H03M13/1111 ,  H03M13/1108 ,  H03M13/3707 ,  H03M13/451 ,  H03M13/458 ,  H04L1/0045 ,  H04L1/0057

Abstract: A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

Abstract translation: 解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。 第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。 第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

公开(公告)号：US20100115377A1

公开(公告)日：2010-05-06

申请号：US12607768

申请日：2009-10-28

Applicant: Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

Inventor： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1108 ,  G06F11/1072

Abstract: A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.

Abstract translation: 至少由纠错码（ECC）解码器和控制器实施的方法估计和校正存储器单元中的错误。 该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

公开(公告)号：US20100091578A1

公开(公告)日：2010-04-15

申请号：US12498508

申请日：2009-07-07

Applicant: Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

Inventor： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/16

Abstract: Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

Abstract translation: 非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

公开(公告)号：US20090296486A1

公开(公告)日：2009-12-03

申请号：US12382351

申请日：2009-03-13

Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

Abstract translation: 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。