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公开(公告)号：US20170110653A1
公开(公告)日：2017-04-20
申请号：US15294100
申请日：2016-10-14
Applicant: Boyoung SEO , Seongui SEO , Gwanhyeob KOH , Yongkyu LEE
Inventor： Boyoung SEO , Seongui SEO , Gwanhyeob KOH , Yongkyu LEE
CPC classification number: G11C11/165 , G11C11/161 , G11C11/1675 , H01L27/228
Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.
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Patent Agency Ranking
12.发明申请公开(公告)号：US20170110171A1
公开(公告)日：2017-04-20
申请号：US15293782
申请日：2016-10-14
Applicant: BOYOUNG SEO , Yongkyu LEE , Gwanhyeob KOH , Cheong Jae LEE
Inventor： BOYOUNG SEO , Yongkyu LEE , Gwanhyeob KOH , Cheong Jae LEE
CPC classification number: G11C11/161 , G11C11/1673 , G11C11/1675 , G11C17/02 , H01L27/228 , H01L43/08 , H01L43/10
Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.
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公开(公告)号：US20150357376A1
公开(公告)日：2015-12-10
申请号：US14639183
申请日：2015-03-05
Applicant: Boyoung Seo , Yongkyu Lee , Keemoon Chun
Inventor： Boyoung Seo , Yongkyu Lee , Keemoon Chun
CPC classification number: H01L27/228 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L43/02 , H01L43/08
Abstract: The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.
Abstract translation: 本发明构思提供了包括可变电阻存储器元件的半导体存储器件。 半导体存储器件可以包括设置在距离半导体衬底的第一高度处的第一位线，与半导体衬底相比设置在与第一高度不同的第二高度的第二位线，连接到第一可变电阻存储器元件 到第一位线，以及连接到第二位线的第二可变电阻存储元件。 第一和第二可变电阻存储器元件可以设置在与半导体衬底基本相同的高度处。
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公开(公告)号：US08891316B2
公开(公告)日：2014-11-18
申请号：US13428965
申请日：2012-03-23
Applicant: Boyoung Seo , Yongkyu Lee , Hyucksoo Yang , Yongtae Kim , Byungsup Shim
Inventor： Boyoung Seo , Yongkyu Lee , Hyucksoo Yang , Yongtae Kim , Byungsup Shim
IPC: G11C16/04 , H01L29/423 , H01L29/788 , H01L27/115 , H01L21/28
CPC classification number: G11C16/0425 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3445 , H01L21/28273 , H01L27/11546 , H01L29/42328 , H01L29/7881
Abstract: Nonvolatile memory devices can include a floating gate on a substrate, with a first tunnel insulating film therebetween. A memory gate can be on the floating gate, with a blocking insulating film therebetween. A word line can be located at a first side of both the memory gate and the floating gate, with a second tunnel insulating film therebetween. The first side of the floating gate can protrude beyond the first side of the memory gate toward the word line.
Abstract translation: 非易失性存储器件可以包括衬底上的浮动栅极，其间具有第一隧道绝缘膜。 存储器栅极可以在浮动栅极上，其间具有阻挡绝缘膜。 字线可以位于存储栅极和浮动栅极的第一侧，其间具有第二隧道绝缘膜。 浮动栅极的第一侧可以突出超过存储器栅极的第一侧朝向字线。
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公开(公告)号：US20140313835A1
公开(公告)日：2014-10-23
申请号：US14242406
申请日：2014-04-01
Applicant: Yongkyu Lee , BoGeun KIM
Inventor： Yongkyu Lee , BoGeun KIM
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C16/3418
Abstract: A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another.
Abstract translation: 提供一种半导体存储器件的数据编程方法，其包括使用根据所述写入数据是否被编程在多个非易失性存储器之一中的从多种随机化方法中选择的随机化方法来随机化写入数据; 以及将所述随机写入数据编程在所述多个非易失性存储器中的至少一个中，其中所述多个非易失性存储器具有彼此不同的类型。
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公开(公告)号：US20120243339A1
公开(公告)日：2012-09-27
申请号：US13428965
申请日：2012-03-23
Applicant: Boyoung Seo , Yongkyu Lee , Hyucksoo Yang , Yongtae Kim , Byungsup Shim
Inventor： Boyoung Seo , Yongkyu Lee , Hyucksoo Yang , Yongtae Kim , Byungsup Shim
IPC: G11C16/04 , H01L29/788
CPC classification number: G11C16/0425 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3445 , H01L21/28273 , H01L27/11546 , H01L29/42328 , H01L29/7881
Abstract: Nonvolatile memory devices can include a floating gate on a substrate, with a first tunnel insulating film therebetween. A memory gate can be on the floating gate, with a blocking insulating film therebetween. A word line can be located at a first side of both the memory gate and the floating gate, with a second tunnel insulating film therebetween. The first side of the floating gate can protrude beyond the first side of the memory gate toward the word line.
Abstract translation: 非易失性存储器件可以包括衬底上的浮动栅极，其间具有第一隧道绝缘膜。 存储器栅极可以在浮动栅极上，其间具有阻挡绝缘膜。 字线可以位于存储栅极和浮动栅极的第一侧，其间具有第二隧道绝缘膜。 浮动栅极的第一侧可以突出超过存储器栅极的第一侧朝向字线。
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