公开(公告)号：US07558931B2

公开(公告)日：2009-07-07

申请号：US11228776

申请日：2005-09-16

Applicant: Yoshiteru Ishida ,  Hitoshi Ogawa ,  Atsushi Saito ,  Terumi Takashi

Inventor： Yoshiteru Ishida ,  Hitoshi Ogawa ,  Atsushi Saito ,  Terumi Takashi

IPC: G06F12/00 ,  G06F12/16

CPC classification number: G11B19/04 ,  G11B20/10 ,  G11B27/036 ,  G11B27/322 ,  G11B2220/2516

Abstract: In one embodiment, a write/read apparatus includes an external interface section for data input; an external interface section for data output; a memory for temporarily storing the data that is input through the external interface section for data input and written on the recording medium and the data that is read from the recording medium and sent to the outside through the external interface section for data output; an address generating section for generating unique addresses associated with physical block addresses of the recording medium; a flag generating section for generating flags for prohibiting overwriting of the data to be written on the recording medium; and a processing section for adding the unique addresses generated in the address generating section to the data that is stored in the memory and that is to be written on the recording medium. The data with the addition of the flags generated in the flag generating section and the unique addresses is written on the recording medium.

Abstract translation: 在一个实施例中，写入/读取装置包括用于数据输入的外部接口部分; 用于数据输出的外部接口部分; 存储器，用于临时存储通过外部接口部分输入并写入到记录介质上的数据的数据和从记录介质读取的数据，并通过外部接口部分发送到外部进行数据输出; 地址产生部分，用于产生与记录介质的物理块地址相关联的唯一地址; 标志产生部分，用于产生用于禁止重写要写入记录介质的数据的标志; 以及处理部分，用于将在地址生成部分中生成的唯一地址添加到存储在存储器中并被写入记录介质的数据。 在标志生成部分生成的标志和唯一地址的数据被写入记录介质。

公开(公告)号：US20060047898A1

公开(公告)日：2006-03-02

申请号：US11213319

申请日：2005-08-26

Applicant: Yoshiteru Ishida ,  Hitoshi Ogawa ,  Terumi Takashi

Inventor： Yoshiteru Ishida ,  Hitoshi Ogawa ,  Terumi Takashi

IPC: G06F12/00

CPC classification number: G06F3/0637 ,  G06F3/0623 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0674 ,  G06F21/80 ,  G11B20/00086 ,  G11B20/00137 ,  G11B20/00615

Abstract: Embodiment of the present invention provide a technique for carrying out work in a short time to prevent without fail data stored in a read/write device from leaking to persons other than an authorized user. There are provided a read/write device, and a format management method for managing a format of data stored in the read/write device. A given change factor is specified for a format of data stored in the read/write device. A format change judgment part for judging whether or not the change factor exists is provided in the read/write device or in a host device connected to the read/write device. Then, a given offset coefficient is generated for a format table according to an instruction from a format change judgment part, and a different format table is generated according to the generated offset coefficient and the format table.

Abstract translation: 本发明的实施例提供了一种用于在短时间内进行工作以防止存储在读/写装置中的数据泄漏给除了授权用户以外的人的技术。 提供了读/写设备和用于管理存储在读/写设备中的数据的格式的格式管理方法。 对于存储在读/写设备中的数据的格式指定给定的变化因子。 用于判断存在变化因素的格式变化判断部分是否被提供在读/写设备或连接到读/写设备的主设备中。 然后，根据来自格式变更判定部的指示，对于格式表生成给定的偏移系数，根据生成的偏移系数和格式表生成不同的格式表。

公开(公告)号：US5878097A

公开(公告)日：1999-03-02

申请号：US865704

申请日：1997-05-30

Applicant: Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

Inventor： Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

IPC: G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  H03H11/26 ,  H03H11/54 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H04L7/00 ,  H04L7/02 ,  H04L25/36 ,  H04L25/40

CPC classification number: H03L7/0805 ,  G11B20/10 ,  G11B20/1403 ,  H03K5/13 ,  H03L7/0812 ,  H03L7/0896 ,  H03L7/0995 ,  H04L7/02 ,  H04L7/0008 ,  H04L7/0041

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

Abstract translation: 制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。 在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。 采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。 这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。 窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。 数据采集​​电路和数据写入电路各自包括模拟可变延迟电路。