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16 条记录 (耗时 0.014 秒)

    Linear transfer voltage to current circuit
    1.
    发明授权
    Linear transfer voltage to current circuit 失效
    线性传输电压到电流电路

    公开(公告)号：US5963064A

    公开(公告)日：1999-10-05

    申请号：US8424

    申请日：1998-01-16

    申请人： Kenji Toyota ,  Tatsuji Matsuura ,  Kenichi Hase

    发明人： Kenji Toyota ,  Tatsuji Matsuura ,  Kenichi Hase

    IPC分类号： H03F3/45 ,  G05F1/56 ,  H03F1/32 ,  H03G3/10 ,  H03G3/30 ,  H02M11/00

    CPC分类号： G05F1/561 ,  H03F1/3211 ,  H03F3/45179

    摘要： A differential circuit having a relatively simple structure capable of delivering a linear transfer characteristic and expanding an input dynamic range. An increase in magnitude of differential input voltage V.sub.in applied to each gate of differential-pair MOSFETs M1 and M2 in the differential circuit decreases control voltage V.sub.CONT in a control circuit. On the other hand, since a current fed to MOSFETs M3 and M4 in the differential circuit decreases simultaneously, a current supplied to the differential-pair MOSFETs M1 and M2 in the differential circuit increases. Thus, the present invention makes it possible to effectively expand the input dynamic range with respect to differential input voltage V.sub.in.

    摘要翻译： 一种具有相对简单结构的差分电路，能够传递线性传递特性并扩大输入动态范围。 施加到差分电路中的差分对MOSFET M1和M2的每个栅极的差分输入电压Vin的幅度的增加降低了控制电路中的控制电压VCONT。 另一方面，由于馈入差分电路中的MOSFET M3和M4的电流同时减小，所以提供给差分电路中的差分对MOSFET M1和M2的电流增加。 因此，本发明使得可以相对于差分输入电压Vin有效地扩展输入动态范围。

    Signal processing delay circuit
    4.
    发明授权
    Signal processing delay circuit 失效
    信号处理延迟电路

    公开(公告)号：US5636254A

    公开(公告)日：1997-06-03

    申请号：US430534

    申请日：1995-04-25

    申请人： Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

    发明人： Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

    IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  H03H11/26 ,  H03H11/54 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H04L7/00 ,  H04L7/02

    CPC分类号： H03L7/0805 ,  G11B20/10 ,  G11B20/1403 ,  H03K5/13 ,  H03L7/0812 ,  H03L7/0896 ,  H03L7/0995 ,  H04L7/02 ,  H04L7/0008 ,  H04L7/0041

    摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

    摘要翻译： 制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。 在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。 采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。 这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。 窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。 数据采集​​电路和数据写入电路各自包括模拟可变延迟电路。

    Disk recording apparatus with adaptive window adjusting
    5.
    发明授权
    Disk recording apparatus with adaptive window adjusting 失效
    具有自适应窗口调节的磁盘记录装置

    公开(公告)号：US5559645A

    公开(公告)日：1996-09-24

    申请号：US216606

    申请日：1994-03-23

    申请人： Shyoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Satoshi Kawamura ,  Shinichi Kojima ,  Toshiyuki Iseki

    发明人： Shyoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Satoshi Kawamura ,  Shinichi Kojima ,  Toshiyuki Iseki

    IPC分类号： G11B5/012 ,  G11B7/0045 ,  G11B20/10 ,  G11B20/14 ,  G11B5/09

    CPC分类号： G11B20/10212 ,  G11B20/1403 ,  G11B5/012 ,  G11B7/0045

    摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

    摘要翻译： 在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机 集成电路。 数据分离器将同步时钟与从盘再现的代码数据分离。 码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。 代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。 写补偿电路相对于写代码数据补偿峰移。 该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。

    Address mark generating method and its circuit in a data memory
    6.
    发明授权
    Address mark generating method and its circuit in a data memory 失效
    地址标记生成方法及其在数据存储器中的电路

    公开(公告)号：US5062011A

    公开(公告)日：1991-10-29

    申请号：US327757

    申请日：1989-03-23

    申请人： Kenichi Hase ,  Shyoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akira Uragami ,  Takashi Watanabe ,  Yoshinori Yoshino

    发明人： Kenichi Hase ,  Shyoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akira Uragami ,  Takashi Watanabe ,  Yoshinori Yoshino

    IPC分类号： G11B20/10 ,  G11B20/14 ,  G11B27/30

    CPC分类号： G11B27/3027 ,  G11B20/1419 ,  G11B20/1426

    摘要： When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.

    摘要翻译： 当使用扇区格式将数据存储在盘形存储介质上的2-7 RLL代码中时，作为每个扇区中的地址标记，使用2-7非法模式; NRZ信号中的1字节数据“8B”被转换为2-7 RLL码，并进一步修改为2-7非法码型。 盘存储器中的盘控制器将1字节数据“8B”插入NRZ信号中的指定位置并将其发送到编码器/解码器。 在编码器中，检测到NRZ信号中的1字节数据“8B”，并且通过将通过转换1字节数据“8B”形成的2-7 RLL码的指定位反转来形成2-7非法模式 “，并且非法模式被发送到读/写放大器。

    Magnetic disk storage apparatus
    7.
    发明授权
    Magnetic disk storage apparatus 失效
    磁盘存储装置

    公开(公告)号：US06266200B1

    公开(公告)日：2001-07-24

    申请号：US09438510

    申请日：1999-11-12

    申请人： Kenichi Hase ,  Syoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akihiko Hirano ,  Akira Uragami

    发明人： Kenichi Hase ,  Syoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akihiko Hirano ,  Akira Uragami

    IPC分类号： G11B509

    CPC分类号： H03L7/093 ,  G11B5/012 ,  G11B20/1403 ,  G11B2020/10916 ,  H03K3/2821 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06 ,  H04L7/033

    摘要： A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium. The processor generates the access position on the magnetic disk-type storage medium and data for commanding the control of the response characteristic of the phase synchronizing circuit in accordance with the information stored in the memory, and commands the control of the response characteristic by the data for the command, at a time consistent with a time of a seek operation of the head for the access position on the magnetic disk-type storage medium or a time before the seek operation of the head. Further, the response characteristic is controlled by the command.

    摘要翻译： 一种具有磁盘式存储介质的磁盘存储装置; 用于读取记录在磁盘式存储介质上的数据的磁头，处理器，具有可控响应特性的相位同步电路，以及用于输出时钟信号以处理从磁盘式存储介质读取的数据的存储器 用于存储用于控制根据磁盘式存储介质上的存取位置预先设定的相位同步电路的响应特性的信息。 处理器根据存储在存储器中的信息产生磁盘式存储介质上的访问位置和用于指示相位同步电路的响应特性的控制的数据，并且通过数据命令对响应特性的控制 在与磁盘式存储介质上的访问位置的头部的寻道操作的时间或头部的搜索操作之前的时间相一致的时间。 此外，响应特性由命令控制。

    Signal processing delay circuit
    8.
    发明授权
    Signal processing delay circuit 失效
    信号处理延迟电路

    公开(公告)号：US5878097A

    公开(公告)日：1999-03-02

    申请号：US865704

    申请日：1997-05-30

    申请人： Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

    发明人： Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

    IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  H03H11/26 ,  H03H11/54 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H04L7/00 ,  H04L7/02 ,  H04L25/36 ,  H04L25/40

    CPC分类号： H03L7/0805 ,  G11B20/10 ,  G11B20/1403 ,  H03K5/13 ,  H03L7/0812 ,  H03L7/0896 ,  H03L7/0995 ,  H04L7/02 ,  H04L7/0008 ,  H04L7/0041

    摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

    摘要翻译： 制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。 在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。 采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。 这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。 窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。 数据采集​​电路和数据写入电路各自包括模拟可变延迟电路。

    Magnetic disk system and waveform equalizer therefor
    9.
    发明授权
    Magnetic disk system and waveform equalizer therefor 失效
    磁盘系统及其波形均衡器

    公开(公告)号：US5463504A

    公开(公告)日：1995-10-31

    申请号：US62770

    申请日：1993-05-18

    申请人： Hiroshi Kimura ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Akihiko Hirano ,  Akira Uragami

    发明人： Hiroshi Kimura ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Akihiko Hirano ,  Akira Uragami

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14

    CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/1403 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1258

    摘要： A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.

    摘要翻译： 根据磁盘上的轨道位置以不同的数据传输速率记录和再现磁盘上的数据的磁盘系统包括对读出波形实现最佳波形整形的横向波形均衡电路。 波形均衡电路由寄存器，频率合成器，PLL和横向电路组成。 横向电路由可变延迟电路，可变增益放大器和加法器组成。 频率合成器产生具有对应于存储在寄存器中的取决于数据传输速率的值的频率的写时钟信号，并且PLL响应于写时钟信号以产生控制信号，通过该控制信号，横向延迟时间 电路被控制。 因此，延迟特性不受横向电路的电路部件的不均匀影响，并且横向电路的写入时钟频率和延迟时间可以通过仅响应于一个变化来改变存储在寄存器中的值来设置为预期值 数据传输速率的变化。