公开(公告)号：US07042041B2

公开(公告)日：2006-05-09

申请号：US10793796

申请日：2004-03-08

申请人： Yuichi Nakashima

发明人： Yuichi Nakashima

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is here disclosed a semiconductor device comprising a capacitor provided on a substrate and formed by sandwiching a capacitive insulating film between lower and upper electrodes, an interlayer insulating film of an n-th layer (n is 1 or greater integer) provided on the substrate to cover the capacitor, and a plurality of plugs and a plurality of wirings provided on the substrate, wherein an electrode wiring among the wirings which is electrically connected to the lower or upper electrode above the capacitor is provided in an interlayer insulating film of an (n+1)-th layer or more formed on the interlayer insulating film of the n-th layer.

摘要翻译： 这里公开了一种半导体器件，其包括设置在基板上并通过将电容绝缘膜夹在下电极和上电极之间而形成的电容器，设置在基板上的第n层（n为1以上整数）的层间绝缘膜 覆盖电容器，以及设置在基板上的多个插头和多个布线，其中在电容器上方电连接到下电极或上电极的布线之间的电极布线设置在（ n + 1）层以上形成在第n层的层间绝缘膜上。

公开(公告)号：US5231041A

公开(公告)日：1993-07-27

申请号：US819206

申请日：1992-01-10

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5101250A

公开(公告)日：1992-03-31

申请号：US630439

申请日：1990-12-20

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US20070228573A1

公开(公告)日：2007-10-04

申请号：US11762432

申请日：2007-06-13

申请人： Takeshi MATSUNAGA ,  Yuichi Nakashima ,  Koji Miyamoto

发明人： Takeshi MATSUNAGA ,  Yuichi Nakashima ,  Koji Miyamoto

IPC分类号： H01L23/52

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

摘要翻译： 一种具有形成在多层布线结构中的电容器的半导体器件，所述半导体器件包括多层布线结构，所述多层布线结构包括形成在基板上的多个布线层，布置在所述多层布线结构中的预定布线层中并具有下电极 介电膜和上电极，形成在预定布线层中并连接到电容器的上电极的顶表面的第一通孔，以及形成在叠置在预定布线层上的上覆布线层中的第二通孔， 第二通孔形成在第一通孔上。

公开(公告)号：US5187558A

公开(公告)日：1993-02-16

申请号：US517628

申请日：1990-05-01

申请人： Yuichi Nakashima ,  Mitsuhiro Tomikawa ,  Hirohisa Yamamoto

发明人： Yuichi Nakashima ,  Mitsuhiro Tomikawa ,  Hirohisa Yamamoto

IPC分类号： H01L23/29 ,  H01L23/31 ,  H01L29/06

CPC分类号： H01L29/0657 ,  H01L23/298 ,  H01L23/3135 ,  H01L23/3178 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041

摘要： A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.

摘要翻译： 树脂密封半导体器件包括形成在基板上并用树脂密封的半导体芯片。 在绝缘绝缘膜和半导体衬底的主表面的边缘之间的半导体衬底的主表面上形成凹部。 该凹部填充有弹性模量小于半导体衬底的材料的缓冲构件。 施加到由树脂的胼los质引起的半导体衬底边缘的机械应力被缓冲构件吸收和减少。 用于隔离的凹部和绝缘膜之间的半导体衬底的一部分防止其余的机械应力从缓冲构件传递到绝缘膜和电路元件。