公开(公告)号：US5323343A

公开(公告)日：1994-06-21

申请号：US77971

申请日：1993-06-18

申请人： Ikuo Ogoh ,  Masao Nagatomo

发明人： Ikuo Ogoh ,  Masao Nagatomo

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/105

摘要： A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.

摘要翻译： 根据本发明的DRAM包括具有由一个传输栅极晶体管（10）和电容器（11）构成的存储单元的存储单元阵列和具有LDD结构的MOS晶体管（45a）的外围电路。 至少连接到传输门晶体管的电容器的源极/漏极区域（19）由低浓度杂质区域（19a）形成。 低浓度杂质区域的杂质浓度基本上等于外围电路的LDD MOS晶体管的低浓度源极/漏极区域（31）的杂质浓度。 传输栅极晶体管的低浓度/漏极区域是通过在高浓度离子注入步骤时对其外围电路的MOS晶体管的高浓度源极/漏极形成的表面进行掩蔽来形成的。 通过省略高浓度离子注入步骤，消除了传输栅晶体管的源极/漏极区的衬底缺陷，以抑制电荷从电容器的泄漏。

公开(公告)号：US5231041A

公开(公告)日：1993-07-27

申请号：US819206

申请日：1992-01-10

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5101250A

公开(公告)日：1992-03-31

申请号：US630439

申请日：1990-12-20

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5849616A

公开(公告)日：1998-12-15

申请号：US770204

申请日：1996-12-19

申请人： Ikuo Ogoh

发明人： Ikuo Ogoh

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/66659 ,  Y10S257/90

摘要： A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors. Due to this structure, the widths of the side wall spacers (21, 22, 27, 28) as diffusion masks which are responsive to required characteristics, are attained for respective side walls of the gate electrodes (17, 18). The semiconductor device of such structure is manufacutred by implanting impurity ions between the steps of forming the first and the second side wall spacers (21, 22, 27, 28) and each time covering prescribed region with a resist film (20, 23, 25, 29, 31, 33, 35).

摘要翻译： 半导体器件包括具有第一和第二场效应晶体管的半导体衬底（11）。 每个晶体管包括形成在半导体衬底上的栅电极（17,18），其间插入有栅极绝缘膜（15,16）。 由栅电极的相对侧壁表面上的一层绝缘膜形成的第一侧壁间隔物（21,22）和源极/漏极区（19,24,26,30），每个包括高和/或低 在半导体衬底（11）的表面上的栅电极（17,18）的杂质浓度区域。 由形成至少所述第二晶体管的栅电极（17,18）的至少一个侧壁表面的绝缘膜的另一层形成的第二侧壁间隔物（27,28）。 第一和/或第二侧壁间隔物（21,22,27,28）形成用于调节晶体管的杂质浓度分布的扩散掩模。 由于这种结构，对于栅电极（17,18）的各个侧壁，获得作为响应所需特性的扩散掩模的侧壁间隔物（21,22,27,28）的宽度。 这种结构的半导体器件通过在形成第一和第二侧壁间隔物（21,22,27,28）的步骤之间注入杂质离子并且每次用抗蚀剂膜（20,23,25）覆盖规定区域来制造 ，29,31,33,35）。

公开(公告)号：US5547885A

公开(公告)日：1996-08-20

申请号：US462938

申请日：1995-06-02

申请人： Ikuo Ogoh

发明人： Ikuo Ogoh

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/66659 ,  Y10S257/90

摘要： A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors. Due to this structure, the widths of the side wall spacers (21, 22, 27, 28) as diffusion masks which are responsive to required characteristics, are attained for respective side walls of the gate electrodes (17, 18). The semiconductor device of such structure is manufactured by implanting impurity ions between the steps of forming the first and the second side wall spacers (21, 22, 27, 28) and each time covering prescribed region with a resist film (20, 23, 25, 29, 31, 33, 35).

摘要翻译： 半导体器件包括具有第一和第二场效应晶体管的半导体衬底（11）。 每个晶体管包括形成在半导体衬底上的栅电极（17,18），其间插入有栅极绝缘膜（15,16）。 由栅电极的相对侧壁表面上的一层绝缘膜形成的第一侧壁间隔物（21,22）和源极/漏极区（19,24,26,30），每个包括高和/或低 在半导体衬底（11）的表面上的栅电极（17,18）的杂质浓度区域。 由形成至少所述第二晶体管的栅电极（17,18）的至少一个侧壁表面的绝缘膜的另一层形成的第二侧壁间隔物（27,28）。 第一和/或第二侧壁间隔物（21,22,27,28）形成用于调节晶体管的杂质浓度分布的扩散掩模。 由于这种结构，对于栅电极（17,18）的各个侧壁，获得作为响应所需特性的扩散掩模的侧壁间隔物（21,22,27,28）的宽度。 这种结构的半导体器件通过在形成第一和第二侧壁间隔物（21,22,27,28）的步骤之间注入杂质离子并且每次用抗蚀剂膜（20,23,25）覆盖规定的区域来制造 ，29,31,33,35）。

公开(公告)号：US5001039A

公开(公告)日：1991-03-19

申请号：US321810

申请日：1989-03-10

申请人： Ikuo Ogoh

发明人： Ikuo Ogoh

IPC分类号： G03F7/40 ,  H01L21/027

CPC分类号： G03F7/40

摘要： A method of forming a resist pattern on a main surface of a semiconductor substrate comprising the steps of exposing a resist to light and developing it to become a predetermined pattern, curing the surface of the resist pattern formed by the exposing and developing treatments by irradiating the surface with far ultraviolet rays having a short wavelength, and baking the resist pattern subjected to a light irradiation treatment. The light irradiation treatment is performed by irradiating the surface of the resist pattern, which is not shaded from light with the far ultraviolet rays, in a state in which a resist pattern region formed on a peripheral portion of the semiconductor substrate is shaded from light. As a result, a crack can be prevented from forming on the resist of the peripheral portion of the semiconductor substrate. A light irradiation apparatus used in the light irradiation treatment comprises shading means for selectively intercepting the irradiation light. The shading means prevent light irradiation onto the resist pattern of the peripheral portion of the semiconductor substrate.

摘要翻译： 一种在半导体衬底的主表面上形成抗蚀剂图案的方法，包括以下步骤：将抗蚀剂曝光并显影成为预定图案，通过曝光和显影处理形成的抗蚀剂图案的表面照射 表面具有短波长的远紫外线，并烘烤经受光照射处理的抗蚀剂图案。 通过在形成在半导体基板的周边部分上形成的抗蚀剂图案区域被遮光的状态下照射不被远紫外线遮蔽的抗蚀剂图案的表面进行光照射处理。 结果，可以防止在半导体衬底的周边部分的抗蚀剂上形成裂纹。 在光照射处理中使用的光照射装置包括用于选择性地截留照射光的遮蔽装置。 遮光装置防止光照射到半导体衬底的周边部分的抗蚀剂图案上。

公开(公告)号：US4903117A

公开(公告)日：1990-02-20

申请号：US203445

申请日：1988-06-07

申请人： Tatsuo Okamoto ,  Ikuo Ogoh

发明人： Tatsuo Okamoto ,  Ikuo Ogoh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41

CPC分类号： H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

摘要： A silicon oxide film and a BPSG film are formed on a silicon substrate to serve as insulating films, and a contact hole is selectively formed in the insulating films. An impurity diffusion layer is formed on the surface layer of the semiconductor substrate at the bottom portion of the contact hole. A second metal film serving as a metal electrode is formed to cover the BPSG film and the impurity diffusion layer, and a first metal film serving as a barrier layer is formed between the second metal film and the BPSG film and impurity diffusion layer. The first metal film prevents boron contained in the BPSG film from being diffused in the second metal film, thereby to prevent precipitation of silicon in the contact hole.

摘要翻译： 在硅衬底上形成氧化硅膜和BPSG膜以用作绝缘膜，并且在绝缘膜中选择性地形成接触孔。 在接触孔的底部的半导体衬底的表面层上形成杂质扩散层。 形成用作金属电极的第二金属膜以覆盖BPSG膜和杂质扩散层，并且在第二金属膜和BPSG膜和杂质扩散层之间形成用作阻挡层的第一金属膜。 第一金属膜防止BPSG膜中含有的硼扩散到第二金属膜中，从而防止硅在接触孔中析出。

公开(公告)号：US5300444A

公开(公告)日：1994-04-05

申请号：US693505

申请日：1991-04-30

申请人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

发明人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

IPC分类号： H01L21/316 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/265

CPC分类号： H01L27/10844 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31612 ,  H01L27/10808

摘要： A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.

摘要翻译： 包括具有堆叠电容器的存储单元的半导体存储器件具有通过选择性去除多晶硅膜（15; 20）和使用相同掩模（14）的氧化硅膜（18a; 18）而形成的堆叠结构。 连接到堆叠电容器的场效应晶体管具有由上述多晶硅膜形成的栅电极（20）。 该多晶硅膜（20）形成在半导体衬底的主表面上。 作为形成在栅电极（20）上的上层绝缘膜的上述氧化硅膜（18）的残留应力为109dyn / cm 2以下。 在使用相同的掩模（14）选择性地去除沉积在其上的多晶硅膜（15）和氧化硅膜（18a）的过程中，在多晶硅膜（20）中没有发生缺口，从而不会降低 该场效应晶体管具有由多晶硅膜形成的栅电极（20）。

公开(公告)号：US5075240A

公开(公告)日：1991-12-24

申请号：US509850

申请日：1990-04-17

申请人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

发明人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

IPC分类号： H01L21/265 ,  H01L21/266

CPC分类号： H01L21/266 ,  Y10S438/972

摘要： A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.

摘要翻译： 在离子注入中使用导电抗蚀剂膜作为掩模。 导电抗蚀剂膜的一部分电连接到半导体衬底。 在离子注入中进入导电抗蚀剂膜的离子的电荷流入半导体衬底并在其中消散。

公开(公告)号：US6078079A

公开(公告)日：2000-06-20

申请号：US479454

申请日：1995-06-07

申请人： Ikuo Ogoh

发明人： Ikuo Ogoh

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L29/6656 ,  H01L21/823864 ,  H01L27/0922

摘要： Disclosed herein are a structure of and a method of manufacturing a semiconductor device which can relatively readily form a high-concentration impurity layer or a three-layer LDD structure for reducing contact resistance in a source/drain region in high accuracy.In the method of manufacturing a semiconductor device, deposition of an oxide insulating film and anisotropic etching thereof are carried out a plurality of times, and the anisotropic etching is carried out in a state covering one side wall of a gate electrode part with a mask at least once in the plurality of times thereby forming side wall spacers having different widths on both side walls of the gate electrode part respectively, while the side wall spacer provided on one of the side walls is employed as a mask to form a high-concentration n-type impurity layer to be inside the source/drain region on a semiconductor substrate surface corresponding to this side.

摘要翻译： 这里公开了可以相对容易地形成高浓度杂质层的半导体器件的结构和制造方法，或者用于以高精度降低源极/漏极区域中的接触电阻的三层LDD结构。 在制造半导体器件的方法中，多次进行氧化物绝缘膜的沉积和各向异性蚀刻，并且以覆盖具有掩模的栅电极部的一个侧壁的状态进行各向异性蚀刻 在多个时间中至少一次，从而分别在栅极电极部分的两个侧壁上形成具有不同宽度的侧壁间隔物，同时将设置在一个侧壁上的侧壁间隔件用作掩模以形成高浓度n 型杂质层位于与该侧对应的半导体衬底表面上的源/漏区内。