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公开(公告)号：US20240004815A1
公开(公告)日：2024-01-04
申请号：US17853842
申请日：2022-06-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Tresidder , Benjamin Tsien
IPC: G06F13/364 , G06F9/48
CPC classification number: G06F13/364 , G06F9/4893
Abstract: Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the physical layer of the data link is in a low power state. In another aspect, the indication that the physical layer of a data link is not transferring data is an indication that a data transfer has been completed.
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公开(公告)号：US20200344039A1
公开(公告)日：2020-10-29
申请号：US16709472
申请日：2019-12-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US20190158374A1
公开(公告)日：2019-05-23
申请号：US16118848
申请日：2018-08-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Alexander J. Branover , Thomas James Gibney , Michael J. Tresidder , Nat Barbiero
Abstract: Systems, apparatuses, and methods for enabling localized control of link states in a computing system are disclosed. A computing system includes at least a host processor, a communication fabric, one or more devices, one or more links, and a local link controller to monitor the one or more links. In various implementations, the local link controller detects and controls states of a link without requiring communication with, or intervention by, the host processor. In various implementations, this local control by the link controller includes control over the clock signals provided to the link. For example, the local link controller can directly control the frequency of a clock supplied to the link.In addition, in various implementations the link controller controls the power supplied to the link. For example, the link controller can control the voltage supplied to the link.
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公开(公告)号：US20140062555A1
公开(公告)日：2014-03-06
申请号：US14076020
申请日：2013-11-08
Applicant: Advanced Micro Devices, Inc
Inventor： Michael J. Osborn , Michael J. Tresidder , Aaron J. Grenat , Joseph Kidd , Priyank Parakh , Steven J. Kommrusch
CPC classification number: H03K5/153 , G06F17/5009 , G06F17/5031 , G06F2217/84
Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
Abstract translation: 公开了关于检测和最小化由集成电路中的时钟域交叉（CDC）产生的定时问题的技术。 在各种实施例中，一个或多个定时参数与集成电路中的时钟域之间的路径相关联，其中一个或多个定时参数指定路径的传播延迟。 在一个实施例中，定时参数可以使用配置文件分发到不同的设计阶段。 在一些实施例中，一个或多个参数可以与RTL模型一起使用以模拟沿着路径的数据信号的传播。 在一些实施例中，一个或多个参数可以与网表结合使用，以便为集成电路创建物理设计，其中物理设计包括具有指定的传播延迟的路径的表示。
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公开(公告)号：US11960435B2
公开(公告)日：2024-04-16
申请号：US17692147
申请日：2022-03-10
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Pradeep Jayaraman , Dean Gonzales , Gerald R. Talbot , Ramon A. Mangaser , Michael J. Tresidder , Prasant Kumar Vallur , Srikanth Reddy Gruddanti , Krishna Reddy Mudimela Venkata , David H. McIntyre
IPC: G06F13/42 , H01L25/065
CPC classification number: G06F13/4291 , G06F13/4286 , H01L25/0652
Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
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Patent Agency Ranking
公开(公告)号：US11281280B2
公开(公告)日：2022-03-22
申请号：US16876325
申请日：2020-05-18
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Benjamin Tsien , Michael J. Tresidder , Ivan Yanfeng Wang , Kevin M. Lepak , Ann Ling , Richard M. Born , John P. Petry , Bryan P. Broussard , Eric Christopher Morton
IPC: G06F1/32 , G06F1/3206 , G06F1/3287 , G06F1/3234
Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.
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公开(公告)号：US20210111861A1
公开(公告)日：2021-04-15
申请号：US17128720
申请日：2020-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US20200174962A1
公开(公告)日：2020-06-04
申请号：US16204751
申请日：2018-11-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michael J. Tresidder , Yanfeng Wang , Shiqi Sun
Abstract: A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.
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公开(公告)号：US10656696B1
公开(公告)日：2020-05-19
申请号：US15907719
申请日：2018-02-28
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Benjamin Tsien , Michael J. Tresidder , Ivan Yanfeng Wang , Kevin M. Lepak , Ann Ling , Richard M. Born , John P. Petry , Bryan P. Broussard , Eric Christopher Morton
IPC: G06F1/32 , G06F1/3206 , G06F1/3287 , G06F1/3234
Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.
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公开(公告)号：US10581587B1
公开(公告)日：2020-03-03
申请号：US16397848
申请日：2019-04-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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