-
公开(公告)号：US10382014B2
公开(公告)日：2019-08-13
申请号：US15390397
申请日：2016-12-23
Applicant: ATI TECHNOLOGIES ULC , Advanced Micro Devices, Inc.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC: H03K3/03 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K5/1534 , H03K5/15 , H03L5/00 , H03L7/099 , H03L1/02 , H03L7/085
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
-
公开(公告)号：US20180183413A1
公开(公告)日：2018-06-28
申请号：US15390397
申请日：2016-12-23
Applicant: ATI TECHNOLOGIES ULC , Advanced Micro Devices, Inc.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
CPC classification number: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03K5/1534 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
-
公开(公告)号：US20140201542A1
公开(公告)日：2014-07-17
申请号：US13744234
申请日：2013-01-17
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Steven J. Kommrusch , Alexander J. Branover , Marvin A. Denman
IPC: G06F1/26
Abstract: Methods, apparatus, and fabrication relating to adaptive performance optimization of a plurality of components in view of power consumption and demand, component activity, and thermal events. A method may comprise allocating a first power budget to a first component of an apparatus, wherein the first power budget is less than a maximum power required by the first component; applying at least a portion of a borrowable power budget, wherein the borrowable power budget equals the maximum power required by the first component minus the first power budget, to a second component of the apparatus; and increasing the first power budget of the first component, in response to a first number or more of thermal events occurring in a first time period.
Abstract translation: 鉴于功耗和需求，组件活动和热事件，有关多个组件的自适应性能优化的方法，设备和制造。 一种方法可以包括将第一功率预算分配给设备的第一分量，其中所述第一功率预算小于所述第一分量所需的最大功率; 将所述可借用功率预算的至少一部分应用于所述装置的第二分量，其中所述可借用功率预算等于所述第一分量减去所述第一功率预算所需的最大功率; 以及响应于在第一时间段中发生的第一个或多个热事件来增加第一部件的第一功率预算。
-
公开(公告)号：US09621143B2
公开(公告)日：2017-04-11
申请号：US14076020
申请日：2013-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Osborn , Michael J. Tresidder , Aaron J. Grenat , Joseph Kidd , Priyank Parakh , Steven J. Kommrusch
CPC classification number: H03K5/153 , G06F17/5009 , G06F17/5031 , G06F2217/84
Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
-
公开(公告)号：US08884668B2
公开(公告)日：2014-11-11
申请号：US13857085
申请日：2013-04-04
Applicant: Advanced Micro Devices, Inc.
Inventor： Steven J. Kommrusch , Bill K. C. Kwan
CPC classification number: H03K3/0375
Abstract: Methods, apparatus, and fabrication techniques relating to improved propagation of fuse data through an integrated circuit device during scan shift reset. In some embodiments, the methods comprise loading a first value of at least one fuse bit to an integrated circuit device, during a time period when a clock signal having a first frequency is provided to at least one component of the integrated circuit device; disabling a scan shift after the loading of the first value; inactivating the clock signal after the loading of the first value; propagating the first value of the at least one fuse bit to the at least one component of the integrated circuit device; and reactivating the clock signal after the propagation of the first value.
Abstract translation: 在扫描移位复位期间通过集成电路器件改进熔丝数据传播的方法，装置和制造技术。 在一些实施例中，在具有第一频率的时钟信号被提供给集成电路器件的至少一个部件的时间段期间，该方法包括将至少一个熔丝位的第一值加载到集成电路器件; 在加载第一个值后禁用扫描移位; 在加载第一个值之后使时钟信号失活; 将所述至少一个熔丝位的所述第一值传播到所述集成电路器件的所述至少一个部件; 并且在传播第一值之后重新激活时钟信号。
-
Patent Agency Ranking
公开(公告)号：US20140300395A1
公开(公告)日：2014-10-09
申请号：US13857085
申请日：2013-04-04
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Steven J. Kommrusch , Bill K.C. Kwan
IPC: H03K3/012
CPC classification number: H03K3/0375
Abstract: Methods, apparatus, and fabrication techniques relating to improved propagation of fuse data through an integrated circuit device during scan shift reset. In some embodiments, the methods comprise loading a first value of at least one fuse bit to an integrated circuit device, during a time period when a clock signal having a first frequency is provided to at least one component of the integrated circuit device; disabling a scan shift after the loading of the first value; inactivating the clock signal after the loading of the first value; propagating the first value of the at least one fuse bit to the at least one component of the integrated circuit device; and reactivating the clock signal after the propagation of the first value.
Abstract translation: 在扫描移位复位期间通过集成电路器件改进熔丝数据传播的方法，装置和制造技术。 在一些实施例中，在具有第一频率的时钟信号被提供给集成电路器件的至少一个部件的时间段期间，所述方法包括将至少一个熔丝位的第一值加载到集成电路器件; 在加载第一个值后禁用扫描移位; 在加载第一个值之后使时钟信号失活; 将所述至少一个熔丝位的所述第一值传播到所述集成电路器件的所述至少一个部件; 并且在传播第一值之后重新激活时钟信号。
-
公开(公告)号：US11936382B2
公开(公告)日：2024-03-19
申请号：US16454596
申请日：2019-06-27
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC: H03L1/02 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K3/03 , H03K5/15 , H03L5/00 , H03L7/085 , H03L7/099 , H03K5/1534
CPC classification number: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997 , H03K5/1534
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
-
公开(公告)号：US08884663B2
公开(公告)日：2014-11-11
申请号：US13776489
申请日：2013-02-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Steven J. Kommrusch , Zihno Jusufovic
CPC classification number: H03K21/023 , G06F1/10 , H03K5/135 , H03K19/00346
Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.
Abstract translation: 与集成电路的时钟树中由电容产生的噪声的管理相关的方法，装置和制造技术。 在一些实施例中，所述方法包括接收信号以将具有第一速率的时钟调整到第二速率; 并且响应于接收到所述信号而将所述时钟从所述第一速率斜升到所述第二速率，其中所述斜坡包括将所述时钟的频率改变为所述第一和第二速率之间的至少三分之一速率。
-
公开(公告)号：US20140240009A1
公开(公告)日：2014-08-28
申请号：US13776489
申请日：2013-02-25
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Steven J. Kommrusch , Zihno Jusufovic
IPC: H03K21/02
CPC classification number: H03K21/023 , G06F1/10 , H03K5/135 , H03K19/00346
Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.
Abstract translation: 与集成电路的时钟树中由电容产生的噪声的管理相关的方法，装置和制造技术。 在一些实施例中，所述方法包括接收信号以将具有第一速率的时钟调整到第二速率; 并且响应于接收到所述信号而将所述时钟从所述第一速率斜升到所述第二速率，其中所述斜坡包括将所述时钟的频率改变为所述第一速率与所述第二速率之间的至少三分之一速率。
-
公开(公告)号：US20140062555A1
公开(公告)日：2014-03-06
申请号：US14076020
申请日：2013-11-08
Applicant: Advanced Micro Devices, Inc
Inventor： Michael J. Osborn , Michael J. Tresidder , Aaron J. Grenat , Joseph Kidd , Priyank Parakh , Steven J. Kommrusch
CPC classification number: H03K5/153 , G06F17/5009 , G06F17/5031 , G06F2217/84
Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
Abstract translation: 公开了关于检测和最小化由集成电路中的时钟域交叉（CDC）产生的定时问题的技术。 在各种实施例中，一个或多个定时参数与集成电路中的时钟域之间的路径相关联，其中一个或多个定时参数指定路径的传播延迟。 在一个实施例中，定时参数可以使用配置文件分发到不同的设计阶段。 在一些实施例中，一个或多个参数可以与RTL模型一起使用以模拟沿着路径的数据信号的传播。 在一些实施例中，一个或多个参数可以与网表结合使用，以便为集成电路创建物理设计，其中物理设计包括具有指定的传播延迟的路径的表示。
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.016 seconds)
