公开(公告)号：US20230402448A1

公开(公告)日：2023-12-14

申请号：US17806903

申请日：2022-06-14

Applicant: Analog Devices, Inc.

Inventor： Sirui Luo ,  Srivatsan Parthasarathy ,  Piotr Olejarz ,  Daniel Boyko ,  Ara Arakelian ,  Stuart Patterson

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H02H9/046

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

公开(公告)号：US20180226788A1

公开(公告)日：2018-08-09

申请号：US15428535

申请日：2017-02-09

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Linfeng He ,  Yuanzhong Zhou

IPC: H02H7/20 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

CPC classification number: H02H7/205 ,  H01L23/5286 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0921

Abstract: Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

公开(公告)号：US09831666B2

公开(公告)日：2017-11-28

申请号：US14797770

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

公开(公告)号：US20160336740A1

公开(公告)日：2016-11-17

申请号：US14797770

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

Abstract translation: 提供射频电路的静电放电（ESD）保护装置和方法。 在某些配置中，集成电路包括第一引脚，第二引脚，正向ESD保护电路和反向ESD保护电路。 正向ESD保护电路包括一个或多个P + / N-EPI二极管，一个或多个ESD保护器件以及串联在第一引脚和第二引脚之间电连接的一个或多个P-EPI / N +二极管。 一个或多个P + / N-EPI二极管的第一P + / N-EPI二极管包括电连接到第一引脚的阳极。 反向ESD保护电路包括一个或多个P + / N-EPI二极管，一个或多个ESD保护器件以及串联在第二引脚和第一引脚之间电连接的一个或多个P-EPI / N +二极管。 一个或多个P-EPI / N +二极管的第一P-EPI / N +二极管包括电连接到第一引脚的阴极。

公开(公告)号：US09184098B2

公开(公告)日：2015-11-10

申请号：US13625577

申请日：2012-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Shuyun Zhang

IPC: H01L29/778 ,  H01L21/8252 ,  H01L27/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract translation: 在第一端子和第二端子之间设置包括多栅极高电子迁移率晶体管（HEMT），正向传导控制块和反向导通控制块的保护电路。 多栅极HEMT包括显式漏极/源极，第一耗尽模式（D模式）栅极，第一增强模式（E模式）栅极，第二E模式栅极，第二D模式栅极， 和明确的源/漏。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 当第一和第二端子之间的电压差大于正向传导触发电压时，正向传导控制块导通第二E模式栅极，当反向导通控制模块的电压差 比反向传导触发电压更负。

公开(公告)号：US20150070806A1

公开(公告)日：2015-03-12

申请号：US14024426

申请日：2013-09-11

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H02H9/046

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

Abstract translation: 公开了与瞬时电气事件相关的主动检测，定时和保护的装置和方法。 检测电路响应瞬时电应力产生检测信号。 集成电路的第一和第二驱动器电路，具有一个或多个双极结型晶体管的每个驱动器基于检测信号而激活并产生激活信号。 第一和第二驱动器电路的一个或多个双极结型晶体管被配置为基本横向地跨过相应的基极区域传导电流。 具有上放电元件和下放电元件的放电电路接收激活信号并激活以衰减瞬时电事件。

公开(公告)号：US20130222961A1

公开(公告)日：2013-08-29

申请号：US13863155

申请日：2013-04-15

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier A. Salcedo

IPC: H02H3/22

CPC classification number: H02H3/22 ,  H01L27/0259 ,  H02H9/046

Abstract: Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

Abstract translation: 公开了用于提供瞬时电气事件保护的装置和方法。 在一个实施例中，一种装置包括检测和定时电路，电流放大电路和钳位电路。 检测和定时电路被配置为检测在第一节点处的瞬时电事件的存在或不存在，并且在检测到瞬态电事件时产生第一持续时间的第一电流。 电流放大电路被配置为从检测和定时电路接收第一电流并且放大第一电流以产生第二电流。 钳位电路电连接在第一节点和第二节点之间，并接收用于激活的第二电流。 钳位电路被配置为响应于第二电流来激活第一和第二节点之间的低阻抗路径，并且否则去激活低阻抗路径。

公开(公告)号：US11569658B2

公开(公告)日：2023-01-31

申请号：US16946917

申请日：2020-07-10

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  James Zhao

IPC: H02H9/04 ,  H01L27/02 ,  H02H9/00

Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

公开(公告)号：US20190131787A1

公开(公告)日：2019-05-02

申请号：US15794394

申请日：2017-10-26

Applicant: ANALOG DEVICES, INC.

Inventor： Linfeng He ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H01L27/02 ,  H01L29/74 ,  H01L23/528

Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

公开(公告)号：US10199369B2

公开(公告)日：2019-02-05

申请号：US15060932

申请日：2016-03-04

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H01L27/02 ,  H02H9/04 ,  H03K17/30

Abstract: Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant actively-controlled protection circuit includes a transient overstress detection circuit, a clamp circuit electrically connected between a first node and a second node, a bias circuit that biases the clamp circuit, and a false condition shutdown circuit. The transient overstress detection circuit generates a detection signal indicating whether or not a transient overstress event is detected between the first and second nodes. Additionally, the false condition shutdown circuit generates a false condition shutdown signal based on low pass filtering a voltage difference between the first and second nodes, thereby determining independently whether or not power is present. The bias circuit controls operation of the clamp circuit in an on state or an off state based on the detection signal and the false condition shutdown signal.