公开(公告)号：US20230161700A1

公开(公告)日：2023-05-25

申请号：US18151834

申请日：2023-01-09

Applicant: Apple Inc.

Inventor： Gaurav Garg ,  Sagi Lahav ,  Lital Levy - Rubin ,  Gerard Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion ,  James Vash

IPC: G06F12/06 ,  G06F12/0891 ,  G06F9/46 ,  G06F13/16 ,  G06F12/0831

CPC classification number: G06F12/063 ,  G06F12/0891 ,  G06F9/467 ,  G06F13/1668 ,  G06F12/0835

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

公开(公告)号：US11275616B2

公开(公告)日：2022-03-15

申请号：US16439920

申请日：2019-06-13

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Sridhar Kotha ,  Srinivasa Rangan Sridharan ,  Xiaoming Wang

IPC: G06F9/46 ,  G06F9/50 ,  G06F12/0804

Abstract: A system and method for efficiently allocating resources of destinations to sources conveying requests to the destinations. In various embodiments, a computing system includes multiple sources that generate requests and multiple destinations that service the requests. One or more transaction tables store requests received from the multiple sources. Arbitration logic selects requests and stores them in a processing table. When the logic selects a given request from the processing table, and determines resources for the corresponding destination is unavailable, the logic removes the given request from the processing table and allocates the request in a retry handling queue. When the retry handling queue has no data storage for the request, logic updates a transaction table entry and maintains a count of such occurrences. When the count exceeds a threshold, the logic stalls requests for that source. Requests in the retry handling queue have priority over requests in the transaction tables.

公开(公告)号：US11030102B2

公开(公告)日：2021-06-08

申请号：US16125438

申请日：2018-09-07

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Rong Zhang Hu ,  Xiaoming Wang

IPC: G06F12/0815 ,  G06F12/0855 ,  G06F13/16 ,  G06F13/40

Abstract: Systems, apparatuses, and methods for reducing memory cache control command hops through a fabric are disclosed. A system includes an interconnect fabric, a plurality of transaction processing queues, and a plurality of memory pipelines. Each memory pipeline includes an arbiter, a combined coherence point and memory cache controller unit, and a memory controller coupled to a memory channel. Each combined unit includes a memory cache controller, a memory cache, and a duplicate tag structure. A single arbiter per memory pipeline performs arbitration across the transaction processing queues to select a transaction address to feed the memory pipeline's combined unit. The combined unit performs coherence operations and a memory cache lookup for the selected transaction. Only after processing is completed in the combined unit is the transaction moved out of its transaction processing queue, reducing power consumption caused by data movement through the fabric.

公开(公告)号：US20200081836A1

公开(公告)日：2020-03-12

申请号：US16125438

申请日：2018-09-07

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Rong Zhang Hu ,  Xiaoming Wang

IPC: G06F12/0815 ,  G06F12/0855 ,  G06F13/16 ,  G06F13/40

Abstract: Systems, apparatuses, and methods for reducing memory cache control command hops through a fabric are disclosed. A system includes an interconnect fabric, a plurality of transaction processing queues, and a plurality of memory pipelines. Each memory pipeline includes an arbiter, a combined coherence point and memory cache controller unit, and a memory controller coupled to a memory channel. Each combined unit includes a memory cache controller, a memory cache, and a duplicate tag structure. A single arbiter per memory pipeline performs arbitration across the transaction processing queues to select a transaction address to feed the memory pipeline's combined unit. The combined unit performs coherence operations and a memory cache lookup for the selected transaction. Only after processing is completed in the combined unit is the transaction moved out of its transaction processing queue, reducing power consumption caused by data movement through the fabric.

公开(公告)号：US10417146B1

公开(公告)日：2019-09-17

申请号：US15980713

申请日：2018-05-15

Applicant: Apple Inc.

Inventor： Sridhar Kotha ,  Neeraj Parik ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Xiaoming Wang

IPC: G06F13/16 ,  G06F12/0871 ,  G06F9/50

Abstract: An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.

公开(公告)号：US20180276128A1

公开(公告)日：2018-09-27

申请号：US15996776

申请日：2018-06-04

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Sukalpa Biswas ,  Prashant Jain

IPC: G06F12/0842

CPC classification number: G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

公开(公告)号：US09860841B2

公开(公告)日：2018-01-02

申请号：US14831438

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Munetoshi Fukami ,  Srinivasa R. Sridharan ,  Harshavardhan Kaushikkar

IPC: H04W52/02 ,  H04L12/773 ,  H04L12/855

CPC classification number: H04W52/0251 ,  H04L45/60 ,  H04L47/2466 ,  Y02D70/00 ,  Y02D70/26

Abstract: Techniques are disclosed relating to a split communications fabric topology. In some embodiments, an apparatus includes a communications fabric structure with multiple fabric units. The fabric units may be configured to arbitrate among control packets of different messages. In some embodiments, a processing element is configured to generate a message that includes a control packet and one or more data packets. In some embodiments, the processing element is configured to transmit the control packet to a destination processing element (e.g., a memory controller) via the communications fabric structure and transmit the data packets to a data buffer. In some embodiments, the destination processing element is configured to retrieve the data packets from the data buffer in response to receiving the control packet via the hierarchical fabric structure. In these embodiments, bypassing the fabric structure for data packets may reduce power consumption.

公开(公告)号：US20170242798A1

公开(公告)日：2017-08-24

申请号：US15052000

申请日：2016-02-24

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Sukalpa Biswas ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

公开(公告)号：US20170055218A1

公开(公告)日：2017-02-23

申请号：US14831438

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Munetoshi Fukami ,  Srinivasa R. Sridharan ,  Harshavardhan Kaushikkar

IPC: H04W52/02 ,  H04L12/773

CPC classification number: H04W52/0251 ,  H04L45/60 ,  H04L47/2466 ,  Y02D70/00 ,  Y02D70/26

Abstract: Techniques are disclosed relating to a split communications fabric topology. In some embodiments, an apparatus includes a communications fabric structure with multiple fabric units. The fabric units may be configured to arbitrate among control packets of different messages. In some embodiments, a processing element is configured to generate a message that includes a control packet and one or more data packets. In some embodiments, the processing element is configured to transmit the control packet to a destination processing element (e.g., a memory controller) via the communications fabric structure and transmit the data packets to a data buffer. In some embodiments, the destination processing element is configured to retrieve the data packets from the data buffer in response to receiving the control packet via the hierarchical fabric structure. In these embodiments, bypassing the fabric structure for data packets may reduce power consumption.

Abstract translation: 公开了关于分离通信结构拓扑的技术。 在一些实施例中，装置包括具有多个织物单元的通信结构结构。 结构单元可以被配置为在不同消息的控制分组之间进行仲裁。 在一些实施例中，处理元件被配置为生成包括控制分组和一个或多个数据分组的消息。 在一些实施例中，处理元件被配置为经由通信结构结构将控制分组发送到目的地处理元件（例如，存储器控制器），并将数据分组发送到数据缓冲器。 在一些实施例中，目的地处理元件被配置为响应于经由分层结构结构接收控制分组而从数据缓冲器中检索数据分组。 在这些实施例中，绕过用于数据分组的结构结构可能会降低功耗。

公开(公告)号：US20140310469A1

公开(公告)日：2014-10-16

申请号：US13860885

申请日：2013-04-11

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Harshavardhan Kaushikkar ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F2212/1008 ,  G06F2212/507

Abstract: An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.

Abstract translation: 公开了一种用于处理计算系统中的一致性事务的装置。 该装置可以包括请求队列电路，复制标签电路和存储器接口单元。 请求队列电路可以被配置为根据所接收的读取事务来生成推测性读取请求。 重复标签电路可以被配置为存储来自一个或多个高速缓冲存储器的标签的副本，并且响应于在所接收的读事务中请求的数据被存储在高速缓冲存储器中的确定来生成杀死消息。 存储器接口单元可以被配置为根据失速条件来存储产生的推测性读取请求。 存储的推测性读取请求可以根据失速条件发送到存储器控制器。 存储器接口单元还可以被配置为响应于杀死消息来删除推测性读取请求。