公开(公告)号：US09639143B2

公开(公告)日：2017-05-02

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

公开(公告)号：US20170055218A1

公开(公告)日：2017-02-23

申请号：US14831438

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Munetoshi Fukami ,  Srinivasa R. Sridharan ,  Harshavardhan Kaushikkar

IPC: H04W52/02 ,  H04L12/773

CPC classification number: H04W52/0251 ,  H04L45/60 ,  H04L47/2466 ,  Y02D70/00 ,  Y02D70/26

Abstract: Techniques are disclosed relating to a split communications fabric topology. In some embodiments, an apparatus includes a communications fabric structure with multiple fabric units. The fabric units may be configured to arbitrate among control packets of different messages. In some embodiments, a processing element is configured to generate a message that includes a control packet and one or more data packets. In some embodiments, the processing element is configured to transmit the control packet to a destination processing element (e.g., a memory controller) via the communications fabric structure and transmit the data packets to a data buffer. In some embodiments, the destination processing element is configured to retrieve the data packets from the data buffer in response to receiving the control packet via the hierarchical fabric structure. In these embodiments, bypassing the fabric structure for data packets may reduce power consumption.

Abstract translation: 公开了关于分离通信结构拓扑的技术。 在一些实施例中，装置包括具有多个织物单元的通信结构结构。 结构单元可以被配置为在不同消息的控制分组之间进行仲裁。 在一些实施例中，处理元件被配置为生成包括控制分组和一个或多个数据分组的消息。 在一些实施例中，处理元件被配置为经由通信结构结构将控制分组发送到目的地处理元件（例如，存储器控制器），并将数据分组发送到数据缓冲器。 在一些实施例中，目的地处理元件被配置为响应于经由分层结构结构接收控制分组而从数据缓冲器中检索数据分组。 在这些实施例中，绕过用于数据分组的结构结构可能会降低功耗。

公开(公告)号：US09189435B2

公开(公告)日：2015-11-17

申请号：US13868313

申请日：2013-04-23

Applicant: Apple Inc.

Inventor： Benjamin K. Dodge ,  Deniz Balkan ,  Gurjeet S. Saund ,  Munetoshi Fukami

IPC: G06F13/16 ,  G06F13/368

CPC classification number: G06F13/368 ,  G06F13/16

Abstract: A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.

Abstract translation: 一种用于仲裁的方法和装置。 在一个实施例中，网络中的一个点包括第一和第二仲裁器。 与第一范围内的地址相关联的交易的仲裁在第一仲裁器中进行，而与第二范围内的地址相关联的交易的仲裁在第二仲裁器中进行。 每个事务是具有相应优先级的多个不同事务类型之一。 耦合测量电路以从第一和第二仲裁器接收信息，每个周期指示赢得其各自仲裁的交易类型。 测量电路可以更新与获胜交易的类型相关联的多个信用。 可以将更新的信用数量提供给第一和第二仲裁器，并且可以用作下一周期中的仲裁的基础。

公开(公告)号：US09182811B2

公开(公告)日：2015-11-10

申请号：US13719535

申请日：2012-12-19

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Gurjeet S Saund ,  Munetoshi Fukami ,  Shane J Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M Kassoff ,  Kevin C Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

公开(公告)号：US20140167840A1

公开(公告)日：2014-06-19

申请号：US13719517

申请日：2012-12-19

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil

IPC: G05B11/01

CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。 功率管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

公开(公告)号：US10206175B2

公开(公告)日：2019-02-12

申请号：US15817564

申请日：2017-11-20

Applicant: Apple Inc.

Inventor： Munetoshi Fukami ,  Srinivasa R. Sridharan ,  Harshavardhan Kaushikkar

IPC: H04W52/02 ,  H04L12/773 ,  H04L12/855

Abstract: Techniques are disclosed relating to a split communications fabric topology. In some embodiments, an apparatus includes a communications fabric structure with multiple fabric units. The fabric units may be configured to arbitrate among control packets of different messages. In some embodiments, a processing element is configured to generate a message that includes a control packet and one or more data packets. In some embodiments, the processing element is configured to transmit the control packet to a destination processing element (e.g., a memory controller) via the communications fabric structure and transmit the data packets to a data buffer. In some embodiments, the destination processing element is configured to retrieve the data packets from the data buffer in response to receiving the control packet via the hierarchical fabric structure. In these embodiments, bypassing the fabric structure for data packets may reduce power consumption.

公开(公告)号：US20180077649A1

公开(公告)日：2018-03-15

申请号：US15817564

申请日：2017-11-20

Applicant: Apple Inc.

Inventor： Munetoshi Fukami ,  Srinivasa R. Sridharan ,  Harshavardhan Kaushikkar

IPC: H04W52/02 ,  H04L12/773 ,  H04L12/855

CPC classification number: H04W52/0251 ,  H04L45/60 ,  H04L47/2466 ,  Y02D70/00 ,  Y02D70/26

Abstract: Techniques are disclosed relating to a split communications fabric topology. In some embodiments, an apparatus includes a communications fabric structure with multiple fabric units. The fabric units may be configured to arbitrate among control packets of different messages. In some embodiments, a processing element is configured to generate a message that includes a control packet and one or more data packets. In some embodiments, the processing element is configured to transmit the control packet to a destination processing element (e.g., a memory controller) via the communications fabric structure and transmit the data packets to a data buffer. In some embodiments, the destination processing element is configured to retrieve the data packets from the data buffer in response to receiving the control packet via the hierarchical fabric structure. In these embodiments, bypassing the fabric structure for data packets may reduce power consumption.

公开(公告)号：US20160328322A1

公开(公告)日：2016-11-10

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/08 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

Abstract translation: 公开了一种用于处理来自计算系统中的功能单元的存储器请求的装置。 该装置可以包括可被配置为从功能接收请求的接口。 响应于确定接收到的请求是来自存储器的数据的请求，可以将电路配置为向存储器发起推测性读取访问命令。 电路还可以被配置为与推测性读取访问并行地确定如果推测性读取将导致排序或一致性违规。

公开(公告)号：US20140317323A1

公开(公告)日：2014-10-23

申请号：US13868313

申请日：2013-04-23

Applicant: APPLE INC.

Inventor： Benjamin K. Dodge ,  Deniz Balkan ,  Gurjeet S. Saund ,  Munetoshi Fukami

IPC: G06F13/368

CPC classification number: G06F13/368 ,  G06F13/16

Abstract: A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.

Abstract translation: 一种用于仲裁的方法和装置。 在一个实施例中，网络中的一个点包括第一和第二仲裁器。 与第一范围内的地址相关联的交易的仲裁在第一仲裁器中进行，而与第二范围内的地址相关联的交易的仲裁在第二仲裁器中进行。 每个事务是具有相应优先级的多个不同事务类型之一。 耦合测量电路以从第一和第二仲裁器接收信息，每个周期指示赢得其各自仲裁的交易的类型。 测量电路可以更新与获胜交易的类型相关联的多个信用。 可以将更新的信用数量提供给第一和第二仲裁器，并且可以用作下一周期中的仲裁的基础。

公开(公告)号：US20140310437A1

公开(公告)日：2014-10-16

申请号：US13861696

申请日：2013-04-12

Applicant: APPLE INC.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Munetoshi Fukami

IPC: G06F13/37

CPC classification number: G06F13/37 ,  G06F13/36

Abstract: In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction.

Abstract translation: 在一个实施例中，仲裁器可以实现具有延迟加权重载机制的赤字加权循环方案。 所述延迟可以大于或等于所述织物时钟与不具有交易但具有未消耗权重（或交易速率的差别的另一措施）的一个或多个源相关联的较慢时钟的比率。 如果在延迟期间从一个或多个源提供事务，则可以防止权重的重新加载。 在一些实施例中，仲裁器可以被扩充以改善在一些接口上的带宽的使用，其中一些事务可能被限制一段时间。 仲裁器可以实现执行循环仲裁的第一个指针。 如果第一指针指示其事务被临时阻止的源，则第二指针可以从主指针的当前位置向前搜索以定位未阻塞的事务。