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    NEXT FETCH PREDICTOR RETURN ADDRESS STACK
    11.
    发明申请
    NEXT FETCH PREDICTOR RETURN ADDRESS STACK 有权
    下一个FETCH PREDICTOR返回地址堆栈

    公开(公告)号：US20140344558A1

    公开(公告)日：2014-11-20

    申请号：US13893898

    申请日：2013-05-14

    Applicant: Apple Inc.

    Inventor： Douglas C. Holman ,  Ramesh B. Gunna ,  Conrado Blasco-Allue

    IPC: G06F9/38

    CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/382 ,  G06F9/3848

    Abstract: A system and method for efficient branch prediction. A processor includes a next fetch predictor to generate a fast branch prediction for branch instructions at an early pipeline stage. The processor also includes a main return address stack (RAS) at a later pipeline stage for predicting the target of return instructions. When a return instruction is encountered, the prediction from the next fetch predictor is replaced by the top of the main RAS. If there are any recent call or return instructions in flight toward the main RAS, then a separate prediction is generated by a mini-RAS.

    Abstract translation: 一种有效的分支预测的系统和方法。 处理器包括下一个提取预测器，用于在早期流水线阶段生成分支指令的快速分支预测。 该处理器还包括在稍后流水线阶段的主返回地址堆栈（RAS），用于预测返回指令的目标。 当遇到返回指令时，来自下一个提取预测器的预测由主RAS的顶部代替。 如果飞行中有最近的呼叫或返回指令进入主RAS，则由小型RAS产生单独的预测。

    Power Sense Correction for Power Budget Estimator
    12.
    发明申请
    Power Sense Correction for Power Budget Estimator 有权

    公开(公告)号：US20220091649A1

    公开(公告)日：2022-03-24

    申请号：US17026121

    申请日：2020-09-18

    Applicant: Apple Inc.

    Inventor： Matthias Knoth ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Ramesh B. Gunna

    IPC: G06F1/28 ,  G06F1/3228 ,  G06Q50/06

    Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

    Method and Apparatus for Reducing Capacitor-Induced Noise
    15.
    发明申请
    Method and Apparatus for Reducing Capacitor-Induced Noise 审中-公开

    公开(公告)号：US20190086942A1

    公开(公告)日：2019-03-21

    申请号：US15708229

    申请日：2017-09-19

    Applicant: Apple Inc.

    Inventor： Jong-Suk Lee ,  Ramesh B. Gunna ,  Shih-Chieh Wen

    IPC: G05F1/46 ,  H03K5/04

    CPC classification number: G05F1/46 ,  G06F1/26 ,  H03K5/04 ,  H03K19/00346

    Abstract: A method and apparatus for reducing capacitor noise in electronic systems is disclosed. A system includes at least one functional circuit block coupled to receive a variable supply voltage. The value of the supply voltage is controlled by a power management circuit. Changing a performance state of the functional circuit block includes increasing the supply voltage for higher performance, and reducing the supply voltage for reduced performance demands. The power management circuit, in changing to a higher performance state, increases the supply voltage at a first rate. A rate control circuit causes the power management circuit to reduce the supply voltage, when changing to a lower performance state, at a second rate that is less than the first rate.

    Next fetch predictor return address stack
    16.
    发明授权
    Next fetch predictor return address stack 有权
    下一个提取预测器返回地址堆栈

    公开(公告)号：US09405544B2

    公开(公告)日：2016-08-02

    申请号：US13893898

    申请日：2013-05-14

    Applicant: Apple Inc.

    Inventor： Douglas C. Holman ,  Ramesh B. Gunna ,  Conrado Blasco-Allue

    IPC: G06F7/38 ,  G06F9/00 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/382 ,  G06F9/3848

    Abstract: A system and method for efficient branch prediction. A processor includes a next fetch predictor to generate a fast branch prediction for branch instructions at an early pipeline stage. The processor also includes a main return address stack (RAS) at a later pipeline stage for predicting the target of return instructions. When a return instruction is encountered, the prediction from the next fetch predictor is replaced by the top of the main RAS. If there are any recent call or return instructions in flight toward the main RAS, then a separate prediction is generated by a mini-RAS.

    Abstract translation: 一种有效的分支预测的系统和方法。 处理器包括下一个提取预测器，用于在早期流水线阶段生成分支指令的快速分支预测。 该处理器还包括在稍后流水线阶段的主返回地址堆栈（RAS），用于预测返回指令的目标。 当遇到返回指令时，来自下一个提取预测器的预测由主RAS的顶部代替。 如果飞行中有最近的呼叫或返回指令进入主RAS，则由小型RAS产生单独的预测。

    IT INSTRUCTION PRE-DECODE
    17.
    发明申请
    IT INSTRUCTION PRE-DECODE 有权
    IT指令预编译

    公开(公告)号：US20140244976A1

    公开(公告)日：2014-08-28

    申请号：US13774093

    申请日：2013-02-22

    Applicant: APPLE INC.

    Inventor： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

    IPC: G06F9/30

    CPC classification number: G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

    Abstract: Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

    Abstract translation: 用于在IT指令块内处理和预解码分支的各种技术。 指令被取出并缓存在指令高速缓存中，并且生成预解码位以指示IT指令的存在以及IT指令块的可能边界。 如果在IT指令块的可能边界内检测到无条件分支，则无条件分支被视为是条件分支。 无条件分支被发送到分支方向预测器，预测器产生无条件分支的分支方向预测。

    Combining Write Buffer with Dynamically Adjustable Flush Metrics
    18.
    发明申请
    Combining Write Buffer with Dynamically Adjustable Flush Metrics 有权
    将写入缓冲区与动态调整冲洗指标相结合

    公开(公告)号：US20130103906A1

    公开(公告)日：2013-04-25

    申请号：US13709649

    申请日：2012-12-10

    Applicant: Apple Inc.

    Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh B. Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0804

    Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

    Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。 折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

    Scalable Cache Coherency Protocol
    19.
    发明公开
    Scalable Cache Coherency Protocol 审中-公开

    公开(公告)号：US20240273024A1

    公开(公告)日：2024-08-15

    申请号：US18582333

    申请日：2024-02-20

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

    IPC: G06F12/0815 ,  G06F12/0831

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Scalable cache coherency protocol
    20.
    发明授权
    Scalable cache coherency protocol 有权

    公开(公告)号：US11868258B2

    公开(公告)日：2024-01-09

    申请号：US18160575

    申请日：2023-01-27

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

    IPC: G06F12/0815 ,  G06F12/0831

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

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