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    Adaptive thermal control system
    1.
    发明授权
    Adaptive thermal control system 有权

    公开(公告)号：US11347198B2

    公开(公告)日：2022-05-31

    申请号：US17012611

    申请日：2020-09-04

    Applicant: Apple Inc.

    Inventor： Matthias Knoth ,  Ramesh B. Gunna ,  Srikanth Balasubramanian

    IPC: H03M1/06 ,  G05B19/406 ,  H03M1/12 ,  H03M1/46 ,  H04W52/36 ,  G01K3/00 ,  G01K15/00

    Abstract: Systems, apparatuses, and methods for implementing an optimized adaptive thermal control mechanism for an integrated circuit (IC) are described. A control unit receives a digital input value which is representative of a temperature of an IC. The control unit compares the input value to at least two set points. A result of a first comparison determines whether an accumulator is incremented or decremented by a programmable gain value. A result of a second comparison determines whether the accumulator is primed with a preset ramp-up value. The preset ramp-up value is used since the accumulator can take several sensing cycles to reach the optimal control value while thermal gradients can become critical in only a few cycles. The output of the accumulator is provided to an actuator which adjusts parameter(s) to modulate the IC's temperature. The granularity and range of the accumulator matches the granularity and range of the actuator.

    Scalable Cache Coherency Protocol
    2.
    发明申请
    Scalable Cache Coherency Protocol 有权

    公开(公告)号：US20220083472A1

    公开(公告)日：2022-03-17

    申请号：US17315725

    申请日：2021-05-10

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund

    IPC: G06F12/0815

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Combining write buffer with dynamically adjustable flush metrics
    4.
    发明授权
    Combining write buffer with dynamically adjustable flush metrics 有权
    将写入缓冲区与动态可调整的flush指标相结合

    公开(公告)号：US08566528B2

    公开(公告)日：2013-10-22

    申请号：US13709649

    申请日：2012-12-10

    Applicant: Apple Inc.

    Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh B. Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC classification number: G06F12/0891 ,  G06F12/0804

    Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

    Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。 折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

    Power sense correction for power budget estimator
    6.
    发明授权
    Power sense correction for power budget estimator 有权

    公开(公告)号：US11416056B2

    公开(公告)日：2022-08-16

    申请号：US17026121

    申请日：2020-09-18

    Applicant: Apple Inc.

    Inventor： Matthias Knoth ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Ramesh B. Gunna

    IPC: G06F1/28 ,  G06Q50/06 ,  G06F1/3228

    Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

    Method and apparatus for reducing capacitor-induced noise
    8.
    发明授权
    Method and apparatus for reducing capacitor-induced noise 有权

    公开(公告)号：US10416692B2

    公开(公告)日：2019-09-17

    申请号：US15708229

    申请日：2017-09-19

    Applicant: Apple Inc.

    Inventor： Jong-Suk Lee ,  Ramesh B. Gunna ,  Shih-Chieh Wen

    IPC: G05F1/10 ,  G05F1/46 ,  H03K5/04 ,  H03K19/003 ,  G06F1/26

    Abstract: A method and apparatus for reducing capacitor noise in electronic systems is disclosed. A system includes at least one functional circuit block coupled to receive a variable supply voltage. The value of the supply voltage is controlled by a power management circuit. Changing a performance state of the functional circuit block includes increasing the supply voltage for higher performance, and reducing the supply voltage for reduced performance demands. The power management circuit, in changing to a higher performance state, increases the supply voltage at a first rate. A rate control circuit causes the power management circuit to reduce the supply voltage, when changing to a lower performance state, at a second rate that is less than the first rate.

    Single power plane dynamic voltage margin recovery for multiple clock domains
    9.
    发明授权
    Single power plane dynamic voltage margin recovery for multiple clock domains 有权

    公开(公告)号：US10401938B1

    公开(公告)日：2019-09-03

    申请号：US15483178

    申请日：2017-04-10

    Applicant: Apple Inc.

    Inventor： Jong-Suk Lee ,  Ramesh B. Gunna ,  Shih-Chieh R. Wen ,  John H. Mylius

    IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

    Abstract: Systems, apparatuses, and methods for reaching power targets across different clock domains are described. In various embodiments, a first processor complex and a second processor complex operate while powered by a same, single power plane, but with respective clock domains. When a request is detected to change an operating mode of a particular core from one of the processor complexes to an operating mode which does not provide the worst-case power supply load on the single power plane, an amount of voltage margin to recover from the operational voltage is determined based on the second operating mode prior to granting the request and based on each other core in the complexes operating in respective current operating modes. An operational voltage less the determined voltage margin to recover is assigned to the processor complexes while different clock frequencies are assigned to the processor complexes.

    REDUCING POWER CONSUMPTION IN A PROCESSOR
    10.
    发明申请
    REDUCING POWER CONSUMPTION IN A PROCESSOR 审中-公开
    降低处理器中的功耗

    公开(公告)号：US20150169041A1

    公开(公告)日：2015-06-18

    申请号：US14104042

    申请日：2013-12-12

    Applicant: Apple Inc.

    Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

    IPC: G06F1/32 ,  G06F9/38

    CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/3802 ,  G06F9/3806 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

    Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

    Abstract translation: 处理器包括用于禁用分支预测单元的存储器阵列的机构。 处理器可以包括可以包括多个条目的下一个提取预测单元。 每个条目可以对应于下一个指令获取组，并且可以存储对应的下一个提取组是否包括条件分支指令的指示。 响应于下一个提取组不包括条件分支指令的指示，获取预测单元可以被配置为在下一个指令执行周期中禁止分支预测单元的存储器阵列。

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