公开(公告)号：US09953701B1

公开(公告)日：2018-04-24

申请号：US15439899

申请日：2017-02-22

Applicant: ARM Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi ,  Jitendra Dasani

IPC: G11C11/34 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.

公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US20240005985A1

公开(公告)日：2024-01-04

申请号：US18369794

申请日：2023-09-18

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US11763880B2

公开(公告)日：2023-09-19

申请号：US16990951

申请日：2020-08-11

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US11468943B2

公开(公告)日：2022-10-11

申请号：US16942708

申请日：2020-07-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Cyrille Nicolas Dray ,  El Mehdi Boujamaa

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/16 ,  G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

公开(公告)号：US11277133B1

公开(公告)日：2022-03-15

申请号：US17000147

申请日：2020-08-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Tirdad Anthony Takeshian

IPC: H03K19/0185 ,  H03K3/037

Abstract: Various implementations described herein are related to a device having level shifter circuitry configured to receive isolation control signals in a first voltage domain and provide an output signal in a second voltage domain that is different than the first voltage domain. The device may include isolation logic circuitry configured to receive a data input signal in the first voltage domain and then provide the isolation control signals to the level shifter circuitry in the first voltage domain based on the data input signal. The isolation logic circuitry may include control passgates that enable the data input signal to propagate to the level shifter circuitry via the isolation control signals.

公开(公告)号：US20220036938A1

公开(公告)日：2022-02-03

申请号：US16942708

申请日：2020-07-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Cyrille Nicolas Dray ,  El Mehdi Boujamaa

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/16 ,  G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

公开(公告)号：US20210304816A1

公开(公告)日：2021-09-30

申请号：US16990951

申请日：2020-08-11

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US11043262B2

公开(公告)日：2021-06-22

申请号：US15886630

申请日：2018-02-01

Applicant: Arm Limited

Inventor： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC: G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US20210158865A1

公开(公告)日：2021-05-27

申请号：US16698866

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Nicolaas Klarinus Johannes VAN WINKELHOFF ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Hetansh Pareshbhai Shah

IPC: G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.