公开(公告)号：US20170371560A1

公开(公告)日：2017-12-28

申请号：US15593560

申请日：2017-05-12

Applicant: ARM Limited

Inventor： Fergus Wilson MACGARRY ,  Michael Andrew CAMPBELL

IPC: G06F3/06

Abstract: A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed. During the training operation, none of the pending access requests will be issued to the memory device, and accordingly by performing the maintenance operation during this period, the potential impact that the performance of the maintenance operation could have had on the handling of the access requests is avoided.

公开(公告)号：US20170364461A1

公开(公告)日：2017-12-21

申请号：US15612072

申请日：2017-06-02

Applicant: ARM LIMITED

Inventor： Daren CROXFORD ,  Sharjeel SAEED ,  Quinn CARTER ,  Michael Andrew CAMPBELL

IPC: G06F13/16

Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

公开(公告)号：US20220014379A1

公开(公告)日：2022-01-13

申请号：US16925723

申请日：2020-07-10

Applicant: Arm Limited

Inventor： Roberto AVANZI ,  Andreas Lars SANDBERG ,  Michael Andrew CAMPBELL ,  Matthias Lothar BOETTCHER ,  Prakash S. RAMRAKHYANI

IPC: H04L9/32 ,  G06F21/64 ,  G06F21/57 ,  H04W12/06

Abstract: Apparatuses and method are disclosed for protecting the integrity of data stored in a protected area of memory. Data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs. The integrity of the first data block is contingent on the verification authentication code matching the retrieved authentication code.

公开(公告)号：US20180203798A1

公开(公告)日：2018-07-19

申请号：US15407681

申请日：2017-01-17

Applicant: ARM Limited

Inventor： Paul Stanley HUGHES ,  Michael Andrew CAMPBELL

IPC: G06F12/0804 ,  G06F12/0864 ,  G06F12/0875

Abstract: A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided. Allocation control circuitry of the cache is responsive to a cache miss to allocate an entry of the multiple entries in the data caching storage circuitry in dependence on a cache allocation policy. Quality-of-service monitoring circuitry is responsive to a quality-of-service indication to modify the cache allocation policy with respect to allocation of the entry for the requested data item. The behaviour of the cache, in particular regarding allocation and eviction, can therefore be modified in order to seek to maintain a desired quality-of-service for the system in which the cache is found.

公开(公告)号：US20160357688A1

公开(公告)日：2016-12-08

申请号：US14731638

申请日：2015-06-05

Applicant: ARM LIMITED

Inventor： Mark Andrew BRITTAIN ,  Michael Andrew CAMPBELL

IPC: G06F12/14 ,  G06F13/18

CPC classification number: G06F12/1441 ,  G06F13/1631 ,  G06F13/18 ,  G06F2212/1052

Abstract: An apparatus and method are provided for controlling access to a memory device. The apparatus has a pending access requests storage that is used to store access requests waiting to be issued to the memory device, and memory access control circuitry is then used to issue to the memory device access requests selected from the pending access requests storage. Access requests are received at an interface of the apparatus from at least one requesting device, and access request evaluation circuitry within the apparatus is arranged to apply criteria to determine, for a current access request, whether to accept that current access request or reject that current access request. The criteria applied takes account of at least one access timing characteristic of the memory device. The access request evaluation circuitry is responsive to determining that the current access request is to be accepted, to cause that current access request to be stored in the pending access requests storage. However, if instead the access request is rejected, it is prevented from being added to the pending access requests storage at that time, and instead a rejection indication is issued to the requesting device that issued that current access request. This provides a mechanism for significantly improving the performance of the memory device by providing more selectivity as to what access requests are accepted into the pending access requests storage.

Abstract translation: 提供了一种用于控制对存储器件的访问的装置和方法。 该设备具有用于存储等待发出到存储器设备的访问请求的等待访问请求存储器，然后使用存储器访问控制电路向存储器设备发送访问从未决访问请求存储器中选择的请求。 在来自至少一个请求设备的设备的接口处接收访问请求，并且设备内的访问请求评估电路被设置为应用标准来确定当前访问请求是接受当前访问请求还是拒绝该当前访问请求 访问请求。 应用的标准考虑到存储器件的至少一个访问定时特性。 访问请求评估电路响应于确定当前访问请求被接受，以使当前访问请求存储在待处理的访问请求存储中。 然而，如果相反，访问请求被拒绝，则阻止其在该时间被添加到等待访问请求存储器，而是向发出当前访问请求的请求设备发出拒绝指示。 这提供了一种机制，通过提供更多的选择性来显着改善存储器件的性能，这些访问请求被接收到待处理的访问请求存储中。

公开(公告)号：US20160154452A1

公开(公告)日：2016-06-02

申请号：US14557895

申请日：2014-12-02

Applicant: ARM LIMITED

Inventor： Andreas HANSSON ,  Ashley John CRAWFORD ,  Michael Andrew CAMPBELL ,  Stephan DIESTELHORST

IPC: G06F1/32 ,  G06F13/24 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method are provided for controlling the power mode of operation of a memory device. The system includes a processing device for performing processing operations on data, and a memory controller associated with the memory device, the memory device being used to store data for access by the processing device. The memory controller has power mode control circuitry to switch the memory device between different power modes of operation. Further, an interrupt controller is configured to issue an event signal to the processing device to trigger performance of at least one processing operation. On issuing the event signal, the interrupt controller further initiates generation of a wakeup stimulus signal to the power mode control circuitry, and the power mode control circuitry is then arranged to determine whether to change the power mode of operation of the memory device in dependence on the wakeup stimulus signal. By such an approach, the wakeup stimulus signal can provide an early trigger to the power mode control circuitry to exit the memory device from at least one low power mode of operation in anticipation of the performance of the at least one processing operation by the processing device requiring data to be accessed in the memory device.

Abstract translation: 提供了一种用于控制存储器件的功率工作模式的系统和方法。 该系统包括用于对数据执行处理操作的处理装置，以及与存储装置相关联的存储器控​​制器，该存储装置用于存储数据以供处理装置访问。 存储器控制器具有电源模式控制电路，以在不同的功率工作模式之间切换存储​​器件。 此外，中断控制器被配置为向处理设备发出事件信号以触发至少一个处理操作的执行。 在发出事件信号时，中断控制器进一步向功率模式控制电路启动唤醒激励信号的产生，然后将功率模式控制电路设置为根据以下方式确定是否改变存储器件的功率工作模式 唤醒刺激信号。 通过这种方法，唤醒激励信号可以提供早期的触发，使得功率模式控制电路从预期的至少一个低功率操作模式退出存储器件，以期预期处理设备执行至少一个处理操作 要求在存储设备中访问数据。

公开(公告)号：US20140143633A1

公开(公告)日：2014-05-22

申请号：US13681789

申请日：2012-11-20

Applicant: ARM LIMITED

Inventor： Michael Andrew CAMPBELL ,  Timothy Nicholas HAY

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract translation: 一种用于校正从存储器件访问的数据中的错误的装置和方法。 从存储器件读取多个读取符号。 然后从n个数据符号和相关联的m个纠错码符号确定综合征信息。 错误校正电路使用校正子信息来尝试定位包含错误的每个读取符号，并纠正每个读取符号中的每个错误。 错误跟踪电路跟踪哪个存储器区域包含错误的位置的读取符号，并且在检测到错误阈值条件时，将至少一个存储器区域设置为擦除存储器区域。 校正电路将每个读取符号视为包含错误的位置读符号，使得要被定位的读符号不是全部随机分布，并且可以校正多于包含错误的PMAX读符号。