公开(公告)号：US10540248B2

公开(公告)日：2020-01-21

申请号：US15593560

申请日：2017-05-12

Applicant: ARM Limited

Inventor： Fergus Wilson MacGarry ,  Michael Andrew Campbell

IPC: G06F3/06 ,  G06F13/16 ,  G06F11/22 ,  G06F11/10 ,  G11C29/12 ,  G06F11/30

Abstract: A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed.

公开(公告)号：US10339050B2

公开(公告)日：2019-07-02

申请号：US15273743

申请日：2016-09-23

Applicant: ARM Limited

Inventor： Andreas Hansson ,  Wendy Arnott Elsasser ,  Michael Andrew Campbell

IPC: G06F12/06 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0888 ,  G06F13/42

Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.

公开(公告)号：US09785578B2

公开(公告)日：2017-10-10

申请号：US14731638

申请日：2015-06-05

Applicant: ARM LIMITED

Inventor： Mark Andrew Brittain ,  Michael Andrew Campbell

IPC: G06F12/14 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F12/1441 ,  G06F13/1631 ,  G06F13/18 ,  G06F2212/1052

Abstract: An apparatus and method are provided for controlling access to a memory device. The apparatus has a pending access requests storage that is used to store access requests waiting to be issued to the memory device, and memory access control circuitry is then used to issue to the memory device access requests selected from the pending access requests storage. Access requests are received at an interface of the apparatus from at least one requesting device, and access request evaluation circuitry within the apparatus is arranged to apply criteria to determine, for a current access request, whether to accept that current access request or reject that current access request. The criteria applied takes account of at least one access timing characteristic of the memory device. The access request evaluation circuitry is responsive to determining that the current access request is to be accepted, to cause that current access request to be stored in the pending access requests storage. However, if instead the access request is rejected, it is prevented from being added to the pending access requests storage at that time, and instead a rejection indication is issued to the requesting device that issued that current access request. This provides a mechanism for significantly improving the performance of the memory device by providing more selectivity as to what access requests are accepted into the pending access requests storage.

公开(公告)号：US08935592B2

公开(公告)日：2015-01-13

申请号：US13681789

申请日：2012-11-20

Applicant: ARM Limited

Inventor： Michael Andrew Campbell ,  Timothy Nicholas Hay

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract translation: 一种用于校正从存储器件访问的数据中的错误的装置和方法。 从存储器件读取多个读取符号。 然后从n个数据符号和相关联的m个纠错码符号确定综合征信息。 错误校正电路使用校正子信息来尝试定位包含错误的每个读取符号，并纠正每个读取符号中的每个错误。 错误跟踪电路跟踪哪个存储器区域包含错误的位置的读取符号，并且在检测到错误阈值条件时，将至少一个存储器区域设置为擦除存储器区域。 校正电路将每个读取符号视为包含错误的位置读符号，使得要被定位的读符号不是全部随机分布，并且可以校正多于包含错误的PMAX读符号。

公开(公告)号：US11797454B2

公开(公告)日：2023-10-24

申请号：US17532555

申请日：2021-11-22

Applicant: Arm Limited

Inventor： Graeme Leslie Ingram ,  Michael Andrew Campbell

IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/0877

CPC classification number: G06F12/0871 ,  G06F12/0246 ,  G06F12/0808 ,  G06F12/0877

Abstract: The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.

公开(公告)号：US20210255981A1

公开(公告)日：2021-08-19

申请号：US16790112

申请日：2020-02-13

Applicant: Arm Limited

Inventor： Matteo Maria Andreozzi ,  Michael Andrew Campbell ,  Giovanni Stea ,  Raffaele Zippo

IPC: G06F13/40 ,  G06F9/48

Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.

公开(公告)号：US10949292B1

公开(公告)日：2021-03-16

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Michael Andrew Campbell ,  Alexander Alfred Hornung ,  Alex James Waugh ,  Klas Magnus Bruce ,  Richard Roy Grisenthwaite

IPC: G06F11/20 ,  G11C29/08 ,  G06F11/10 ,  G11C29/18 ,  G06F11/30

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US09411774B2

公开(公告)日：2016-08-09

申请号：US13868180

申请日：2013-04-23

Applicant: ARM Limited

Inventor： Michael Andrew Campbell

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/167 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F15/167 ,  G06F12/0207 ,  G06F12/0623 ,  G06F13/1615

Abstract: Memory access circuitry controls access to multiple memory units with two access units. Arbitration circuitry forwards memory access requests for one memory unit to a first access unit, for a further memory unit to a second access unit, and for yet further memory unit to one of the first or second access units. The access units store requests in a queue prior to transmitting them to the respective memory unit. Tracking circuitry tracks requests and determines when to transmit subsequent requests from the queue. Control circuitry sets a state of each access unit to one of active, prepare and dormant, switches states of the two access units periodically, and does not set more than one access unit to the active state at the same time.

Abstract translation: 存储器访问电路控制使用两个访问单元访问多个存储单元。 仲裁电路将用于一个存储器单元的存储器访问请求转发到第一访问单元，将另一个存储器单元转发到第二访问单元，以及将另外的存储器单元转发到第一或第二访问单元之一。 访问单元将请求存储在队列中，然后将它们发送到相应的存储器单元。 跟踪电路跟踪请求并确定何时从队列传送后续请求。 控制电路将每个访问单元的状态设置为两个访问单元的活动，准备和休眠切换状态之一，并且不会同时将多个访问单元设置为活动状态。