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公开(公告)号：US07761676B2
公开(公告)日：2010-07-20
申请号：US11637661
申请日：2006-12-12
IPC分类号： G06F12/00
CPC分类号： G06F12/1466
摘要： In one embodiment, the present invention includes a method for associating a first identifier with a first pointer that points to a first object in a memory. The first identifier may correspond to a value in a segment of a map array for a location of the first object in the memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将第一标识符与指向存储器中的第一对象的第一指针相关联的方法。 第一标识符可以对应于存储器中第一对象的位置的映射数组的段中的值。 描述和要求保护其他实施例。
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公开(公告)号：US20170285975A1
公开(公告)日：2017-10-05
申请号：US15088955
申请日：2016-04-01
申请人： Sanjeev N. Trika , Kshitij A. Doshi
发明人： Sanjeev N. Trika , Kshitij A. Doshi
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0623 , G06F3/0638 , G06F3/0649 , G06F3/0659 , G06F3/0673 , G06F3/0674 , G06F3/0679
摘要： Technologies for managing immutable data include a data storage device having a data storage controller and memory for storing data. The data storage controller may receive requests from a host of the data storage device to mark data stored in the memory as immutable. In response to the request, the data storage controller is configured to set an immutable flag associated with the identified data to mark the identified data as immutable. The immutable flag, when set, provides an indication that the associated data is unmodifiable. In some embodiments, the data storage device may also compact and/or move the immutable data to an immutable memory region of the memory. Technologies to mark the immutable data as mutable, write to the immutable data, and delete or trim the immutable data are also disclosed.
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13.发明申请公开(公告)号：US20170269935A1
公开(公告)日：2017-09-21
申请号：US15612204
申请日：2017-06-02
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/3455
摘要： Instructions and logic provide vector loads and/or stores with stride and mask functionality. In one implementation, a processor is provided that includes decode circuitry to decode an instruction specifying a memory address and a stride length for a set of load operations corresponding to a first plurality of data elements of a destination register. The processor further includes one or more execution units, responsive to the decoded first instruction, to load a first data element from the memory address into a first data element of the destination register, and load a second data element from a memory address that is non-zero multiple of the stride length into a first data element of the destination register.
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公开(公告)号：US09747101B2
公开(公告)日：2017-08-29
申请号：US13977729
申请日：2011-09-26
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30105 , G06F9/30145 , G06F9/3836 , G06F15/8061
摘要： Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.
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公开(公告)号：US09575757B2
公开(公告)日：2017-02-21
申请号：US13991858
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译： 一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。 执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。 第二个掩码基于尾随零的计数。 执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。 将缓冲区移位并复制到结果，并将源数据元素集合向右移动。 如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。
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公开(公告)号：US20140025901A1
公开(公告)日：2014-01-23
申请号：US14033463
申请日：2013-09-21
申请人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
发明人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译： 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。
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公开(公告)号：US20140019714A1
公开(公告)日：2014-01-16
申请号：US13993068
申请日：2011-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30025 , G06F9/30036 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
摘要翻译： 包括硬件解码单元和执行引擎单元的处理器核心。 所述硬件解码单元对矢量频率扩展指令进行解码，其中所述向量频率压缩指令包括源操作数和目的操作数，其中所述源操作数指定源向量寄存器，所述源向量寄存器包括一对或多对值和游程长度， 根据运行长度将其扩展为该值的运行。 执行引擎单元，用于执行解码矢量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及 包括在源向量寄存器中运行长度编码的至少一个相同值的运行。
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公开(公告)号：US20200023842A1
公开(公告)日：2020-01-23
申请号：US16586665
申请日：2019-09-27
申请人： David Gomez Gutierrez , Javier Felip Leon , Kshitij A. Doshi , Leobardo E. Campos Macias , Nilesh Amar Ahuja , Omesh Tickoo
发明人： David Gomez Gutierrez , Javier Felip Leon , Kshitij A. Doshi , Leobardo E. Campos Macias , Nilesh Amar Ahuja , Omesh Tickoo
IPC分类号： B60W30/095 , G06K9/00 , B60W50/14
摘要： An apparatus comprising a memory to store an observed trajectory of a pedestrian, the observed trajectory comprising a plurality of observed locations of the pedestrian over a first plurality of timesteps; and a processor to generate a predicted trajectory of the pedestrian, the predicted trajectory comprising a plurality of predicted locations of the pedestrian over the first plurality of timesteps and over a second plurality of timesteps occurring after the first plurality of timesteps; determine a likelihood of the predicted trajectory based on a comparison of the plurality of predicted locations of the pedestrian over the first plurality of timesteps and the plurality of observed locations of the pedestrian over the first plurality of timesteps; and responsive to the determined likelihood of the predicted trajectory, provide information associated with the predicted trajectory to a vehicle to warn the vehicle of a potential collision with the pedestrian.
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公开(公告)号：US20170286310A1
公开(公告)日：2017-10-05
申请号：US15087162
申请日：2016-03-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0811 , G06F12/0893 , G06F2212/604 , G06F2212/70
摘要： Technologies for region-based cache management includes network computing device. The network computing device is configured to divide an allocated portion main memory of the network computing device into a plurality of memory regions, each memory region having a cache block that includes a plurality of cache lines of a cache memory of the processor. The network computing device is further configured to determine whether a cache line selected for eviction from the cache memory corresponds to one of the plurality of memory regions and, if so, retrieve a dynamically adjustable bias value (i.e., a fractional probability) associated with the corresponding memory region. Additionally, the network computing device is configured to generate a bias comparator value for the corresponding memory region, compare the bias value of the corresponding memory region and the bias comparator value generated for the corresponding memory region, and determine whether to evict the cache line based on the comparison. Other embodiments are described herein.
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公开(公告)号：US20170185643A1
公开(公告)日：2017-06-29
申请号：US14757602
申请日：2015-12-23
IPC分类号： G06F17/30
CPC分类号： G06F16/2379
摘要： Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.
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