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    DYNAMIC CLOCK CONTROL TO INCREASE STUTTER EFFICIENCY IN THE MEMORY SUBSYSTEM
    13.
    发明申请
    DYNAMIC CLOCK CONTROL TO INCREASE STUTTER EFFICIENCY IN THE MEMORY SUBSYSTEM 审中-公开

    公开(公告)号：US20190147926A1

    公开(公告)日：2019-05-16

    申请号：US15809608

    申请日：2017-11-10

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Bradley Kent ,  Joyce C. Wong

    IPC: G11C7/22 ,  G11C7/20 ,  G06F13/16

    Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.

    System and method for monitoring and controlling a performance state change
    14.
    发明授权
    System and method for monitoring and controlling a performance state change 有权

    公开(公告)号：US10146282B2

    公开(公告)日：2018-12-04

    申请号：US14528431

    申请日：2014-10-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

    IPC: G06F1/26 ,  G06F1/32 ,  G06F21/75

    Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request. The system further includes performance state security logic operative to adjust, in response to the request, an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state.

    System and method for secure control over performance state
    15.
    发明授权
    System and method for secure control over performance state 有权
    用于安全控制性能状态的系统和方法

    公开(公告)号：US09396360B2

    公开(公告)日：2016-07-19

    申请号：US13928930

    申请日：2013-06-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

    IPC: G06F3/00 ,  G06F21/81

    CPC classification number: G06F21/81

    Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes intercepting a request for a change of a performance state of the processor and determining whether to execute the request based on a security condition of the processor. The performance state of the processor includes at least one of an operating voltage and an operating frequency. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic in communication with the operating system module and operative to receive the request and to change the performance state of the at least one processing core based on the request. The computing system further includes performance state security logic operative to intercept the request transmitted from the operating system module to the performance state control logic and to selectively transmit the request to the performance state control logic based on a security condition of the computing system.

    Abstract translation: 本公开涉及一种用于确保一个或多个处理器的性能状态改变的方法和系统。 所公开的方法包括拦截对处理器的性能状态的改变的请求，并且基于处理器的安全条件来确定是否执行请求。 处理器的性能状态包括工作电压和工作频率中的至少一个。 所公开的系统包括操作系统模块，其操作以发送对至少一个处理核心的性能状态改变的请求。 该系统包括与操作系统模块通信的性能状态控制逻辑，并且可操作以基于该请求接收该请求并改变至少一个处理核心的性能状态。 计算系统还包括性能状态安全逻辑，其可操作地拦截从操作系统模块发送到性能状态控制逻辑的请求，并且基于计算系统的安全状况来选择性地将该请求发送到性能状态控制逻辑。

    SYSTEM AND METHOD FOR SECURE CONTROL OVER PERFORMANCE STATE
    16.
    发明申请
    SYSTEM AND METHOD FOR SECURE CONTROL OVER PERFORMANCE STATE 有权
    用于在性能状态下进行安全控制的系统和方法

    公开(公告)号：US20150007356A1

    公开(公告)日：2015-01-01

    申请号：US13928930

    申请日：2013-06-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

    IPC: G06F21/81

    CPC classification number: G06F21/81

    Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes intercepting a request for a change of a performance state of the processor and determining whether to execute the request based on a security condition of the processor. The performance state of the processor includes at least one of an operating voltage and an operating frequency. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic in communication with the operating system module and operative to receive the request and to change the performance state of the at least one processing core based on the request. The computing system further includes performance state security logic operative to intercept the request transmitted from the operating system module to the performance state control logic and to selectively transmit the request to the performance state control logic based on a security condition of the computing system.

    Abstract translation: 本公开涉及一种用于确保一个或多个处理器的性能状态改变的方法和系统。 所公开的方法包括拦截对处理器的性能状态的改变的请求，并且基于处理器的安全条件来确定是否执行请求。 处理器的性能状态包括工作电压和工作频率中的至少一个。 所公开的系统包括操作系统模块，其操作以发送对至少一个处理核心的性能状态改变的请求。 该系统包括与操作系统模块通信的性能状态控制逻辑，并且可操作以基于该请求接收该请求并改变至少一个处理核心的性能状态。 计算系统还包括性能状态安全逻辑，其可操作地拦截从操作系统模块发送到性能状态控制逻辑的请求，并且基于计算系统的安全状况来选择性地将该请求发送到性能状态控制逻辑。

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