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    Dynamic Interrupt Rate Control in Computing Systems
    1.
    发明申请
    Dynamic Interrupt Rate Control in Computing Systems 审中-公开

    公开(公告)号：US20190163251A1

    公开(公告)日：2019-05-30

    申请号：US15899157

    申请日：2018-02-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sridhar V. Gada ,  Alexander J. Branover

    IPC: G06F1/32 ,  G06F9/48 ,  G06F9/50

    CPC classification number: G06F1/329 ,  G06F9/4812 ,  G06F9/5027 ,  G06F9/5094

    Abstract: Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.

    Dynamic interrupt rate control in computing system
    3.
    发明授权
    Dynamic interrupt rate control in computing system 有权

    公开(公告)号：US10747298B2

    公开(公告)日：2020-08-18

    申请号：US15899157

    申请日：2018-02-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sridhar V. Gada ,  Alexander J. Branover

    IPC: G06F1/329 ,  G06F9/50 ,  G06F9/48

    Abstract: Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.

    DYNAMIC POWER MANAGEMENT OPTIMIZATION
    7.
    发明申请
    DYNAMIC POWER MANAGEMENT OPTIMIZATION 审中-公开
    动态电源管理优化

    公开(公告)号：US20160378168A1

    公开(公告)日：2016-12-29

    申请号：US14751515

    申请日：2015-06-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Ashish Jain ,  Sridhar V. Gada

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

    Abstract: Systems, apparatuses, and methods for managing power usage of integrated circuits. One or more processor cores may be powered down when the system is idle. Even if there is no user activity, the processor core(s) may be woken up periodically for background downloads to retrieve the latest status for social media and other applications. Additionally, a power management unit may track the average number of active cores and the average core utilization. If the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold, the power management unit may generate a request to offline one or more cores. Still further, when the processor's skin temperature is above a threshold and all of the cores are operating at the lowest acceptable operating point, one or more cores may be powered down.

    Abstract translation: 用于管理集成电路的电力使用的系统，设备和方法。 当系统空闲时，一个或多个处理器内核可能会关闭电源。 即使没有用户活动，也可以周期性地唤醒处理器核心以进行背景下载以检索社交媒体和其他应用程序的最新状态。 此外，电源管理单元可以跟踪活动核心的平均数量和平均核心利用率。 如果活动核心的平均数量小于第一阈值，并且平均核心利用率小于第二阈值，则电源管理单元可以产生离线一个或多个核心的请求。 此外，当处理器的皮肤温度高于阈值并且所有核心都在最低可接受的工作点运行时，一个或多个核心可以掉电。

    Performance State Selection for Low Activity Scenarios
    8.
    发明申请
    Performance State Selection for Low Activity Scenarios 有权
    低活动情景下的绩效状态选择

    公开(公告)号：US20160306406A1

    公开(公告)日：2016-10-20

    申请号：US14846058

    申请日：2015-09-04

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Alexander J. Branover ,  Adam N.C. Clark ,  Ashish Jain ,  Sridhar V. Gada

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

    Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

    Abstract translation: 电力管理控制器跟踪计算单元的空闲状态，并将跟踪的空闲状态与第一阈值进行比较。 如果跟踪的空闲状态高于第一阈值，则计算单元的功率状态被限制为低功率状态，使得由于在低利用场景中发生的活动而导致功率状态不上升。 将跟踪的空闲状态与第二阈值进行比较，并且如果跟踪的空闲状态低于第二阈值，则指示计算单元不处于低利用率场景中，则去除功率状态的限制，并且计算的功率状态 单位被允许上升。

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