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    BATCHING MODIFIED BLOCKS TO THE SAME DRAM PAGE
    11.
    发明申请
    BATCHING MODIFIED BLOCKS TO THE SAME DRAM PAGE 有权
    将修改好的块装入相同的DRAM页面

    公开(公告)号：US20160170887A1

    公开(公告)日：2016-06-16

    申请号：US14569175

    申请日：2014-12-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Syed Ali R. JAFRI ,  Yasuko ECKERT ,  Srilatha MANNE ,  Mithuna S. THOTTETHODI ,  Gabriel H. LOH

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0833 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/62 ,  Y02D10/13

    Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.

    Abstract translation: 为了有效地将数据从高速缓存传输到存储器，期望将与存储器中的相同页面相对应的更多数据加载到行缓冲器中。 将数据写入当前未加载到行缓冲区的内存页面时，需要关闭旧页面并打开新页面。 两种操作都消耗能量和时钟周期，并可能延迟更多关键的存储器读取请求。 因此，期望具有多于一个写入同一DRAM页面的写入以分摊打开和关闭DRAM页面的成本。 期望的方法是通过将修改的块保留在高速缓存中来批量回写到相同的DRAM页面，直到属于同一存储器页面的足够数量的修改的块准备好回写。

    SYSTEM AND METHOD FOR PAGE TABLE CACHING MEMORY
    12.
    发明申请
    SYSTEM AND METHOD FOR PAGE TABLE CACHING MEMORY 有权

    公开(公告)号：US20210097002A1

    公开(公告)日：2021-04-01

    申请号：US16586183

    申请日：2019-09-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Derrick Allen AGUREN ,  Eric H. VAN TASSELL ,  Gabriel H. LOH ,  Jay FLEISCHMAN

    IPC: G06F12/1009 ,  G06F12/14 ,  G06F12/0891 ,  G06F9/455

    Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.

    COHERENCY DIRECTORY ENTRY ALLOCATION BASED ON EVICTION COSTS
    14.
    发明申请
    COHERENCY DIRECTORY ENTRY ALLOCATION BASED ON EVICTION COSTS 审中-公开

    公开(公告)号：US20200065246A1

    公开(公告)日：2020-02-27

    申请号：US16108696

    申请日：2018-08-22

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Michael W. BOYER ,  Gabriel H. LOH ,  Yasuko ECKERT ,  William L. WALKER

    IPC: G06F12/0817 ,  G06F12/0842 ,  G06F11/30

    Abstract: A processor partitions a coherency directory into different regions for different processor cores and manages the number of entries allocated to each region based at least in part on monitored recall costs indicating expected resource costs for reallocating entries. Examples of monitored recall costs include a number of cache evictions associated with entry reallocation, the hit rate of each region of the coherency directory, and the like, or a combination thereof. By managing the entries allocated to each region based on the monitored recall costs, the processor ensures that processor cores associated with denser memory access patterns (that is, memory access patterns that more frequently access cache lines associated with the same memory pages) are assigned more entries of the coherency directory.

    ADDRESS-PARTITIONED MULTI-CLASS PHYSICAL MEMORY SYSTEM
    15.
    发明申请
    ADDRESS-PARTITIONED MULTI-CLASS PHYSICAL MEMORY SYSTEM 审中-公开
    地址分配多类物理存储系统

    公开(公告)号：US20150261662A1

    公开(公告)日：2015-09-17

    申请号：US14206512

    申请日：2014-03-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H. LOH ,  Nuwan S. JAYASENA ,  Michael IGNATOWSKI

    IPC: G06F12/02

    CPC classification number: G06F12/023 ,  G06F12/0284 ,  G06F2212/1044

    Abstract: A multilevel memory system includes a plurality of memories and a processor having a memory controller. The memory controller classifies each memory in accordance with a plurality of memory classes based on its level, its type, or both. The memory controller partitions a unified memory address space into contiguous address blocks and allocates the address blocks among the memory classes. In some implementations, the memory controller then can partition the address blocks assigned to each given memory class into address subblocks and interleave the address subblocks among the memories of the memory class.

    Abstract translation: 多级存储器系统包括多个存储器和具有存储器控制器的处理器。 存储器控制器根据其级别，类型或两者根据多个存储器类别对每个存储器进行分类。 存储器控制器将统一的存储器地址空间划分成连续的地址块，并在存储器类之间分配地址块。 在一些实现中，存储器控制器然后可以将分配给每个给定存储器类的地址块划分为地址子块，并且交织存储器类的存储器中的地址子块。

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