公开(公告)号：US10546949B2

公开(公告)日：2020-01-28

申请号：US14758035

申请日：2013-12-23

Applicant: Agency for Science, Technology and Research

Inventor： Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Hui Ru Tan ,  Sudhiranjan Tripathy

IPC: H01L27/12 ,  H01L29/778 ,  H01L21/02 ,  C30B25/02 ,  C30B29/40 ,  H01L29/66 ,  H01L29/20

Abstract: Contemplated is a semiconductor device comprising: a substrate; a group (III)-nitride layer; a metal-group (III)-nitride layer deposited between the substrate and group (III)-nitride layer; and a metal-nitride layer deposited between the substrate and the metal-group (III)-nitride layer. Also a method for making a semiconductor device with the above mentioned structure is contemplated. Furthermore, the substrate can be a silicon on insulator (SOI) substrate; the metal-nitride layer can be an aluminium nitride layer; the metal-group (III)-nitride layer can be an aluminium gallium nitride layer; and the group (III)-nitride layer can be a gallium nitride layer.

公开(公告)号：US09954088B2

公开(公告)日：2018-04-24

申请号：US15029835

申请日：2014-10-20

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Surani Bin Dolmanan ,  Manippady Krishna Kumar ,  Rasanayagam Sivasayan Kajen ,  Sudhiranjan Tripathy

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/7786 ,  H01L29/78

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

公开(公告)号：US09647183B2

公开(公告)日：2017-05-09

申请号：US14927723

申请日：2015-10-30

Applicant: Agency for Science, Technology and Research

Inventor： Sivashankar Krishnamoorthy ,  Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Siew Lang Teo ,  Sudhiranjan Tripathy

IPC: H01L29/06 ,  H01L31/00 ,  H01L33/58 ,  H01L33/00 ,  H01L33/06 ,  H01L33/10 ,  H01L33/32

CPC classification number: H01L33/58 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/10 ,  H01L33/32 ,  H01L2933/0083

Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer. There is also provided a vertical light emitting diode with the self-assembly derived ordered nanoparticles.