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    USER ASSIGNED NETWORK INTERFACE QUEUES
    11.
    发明公开
    USER ASSIGNED NETWORK INTERFACE QUEUES 审中-公开

    公开(公告)号：US20240111562A1

    公开(公告)日：2024-04-04

    申请号：US17957939

    申请日：2022-09-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Evgeny Schmeilin ,  Dileep Varma Bairraju ,  Georgy Zorik Machulsky ,  Said Bshara

    IPC: G06F9/455

    CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45575

    Abstract: An Application Programming Interface (API) allows a launching of a virtual machine where a queue count can be configured by a user. More specifically, each virtual machine can be assigned a pool of queues. Additionally, each virtual machine can have multiple virtual networking interfaces and a user can assign a number of queues from the pool to each virtual networking interface. Thus, a new metadata field is described that can be used with requests to launch a virtual machine. The metadata field includes one or more parameters that associate a number of queues with each virtual networking interface. A queue count can be dynamically configured by a user to ensure that the queues are efficiently used given that the user understands the intended application of the virtual machine being launched.

    Low-latency packet processing for network device
    12.
    发明授权
    Low-latency packet processing for network device 有权

    公开(公告)号：US11467998B1

    公开(公告)日：2022-10-11

    申请号：US17203231

    申请日：2021-03-16

    Applicant: Amazon Technologies, Inc.

    Inventor： Erez Izenberg ,  Said Bshara ,  Jonathan Cohen ,  Avigdor Segal

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78 ,  G06F9/46

    Abstract: Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

    System and method for managing transactions
    14.
    发明授权
    System and method for managing transactions 有权

    公开(公告)号：US10061700B1

    公开(公告)日：2018-08-28

    申请号：US15230230

    申请日：2016-08-05

    Applicant: Amazon Technologies, Inc.

    Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

    IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0855

    CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

    Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

    LOW LATENCY INTERRUPT WITH EXISTENCE OF INTERRUPT MODERATION
    15.
    发明申请
    LOW LATENCY INTERRUPT WITH EXISTENCE OF INTERRUPT MODERATION 审中-公开

    公开(公告)号：US20170270064A1

    公开(公告)日：2017-09-21

    申请号：US15616832

    申请日：2017-06-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

    IPC: G06F13/24 ,  G06F9/48

    CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F2213/2408

    Abstract: An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.

    Clock synchronization in a network using a distributed pulse signal
    17.
    发明授权
    Clock synchronization in a network using a distributed pulse signal 有权

    公开(公告)号：US11967964B1

    公开(公告)日：2024-04-23

    申请号：US17709939

    申请日：2022-03-31

    Applicant: Amazon Technologies, Inc.

    Inventor： Noam Katz ,  Said Bshara ,  Erez Izenberg ,  Noam Attias

    IPC: H03L7/10 ,  G11C7/10 ,  H03L7/083 ,  H03L7/199

    CPC classification number: H03L7/103 ,  G11C7/1039 ,  H03L7/083 ,  H03L7/199

    Abstract: A clock disciplining scheme uses a pulse per second (PPS) signal that is distributed throughout a network to coordinate timing. In determining the time, jitter can occur due to latency between detection of the PPS signal and a software interrupt generated there from. This jitter affects the accuracy of the clock disciplining process. To eliminate the jitter, extra hardware is used to capture when the PPS signal occurred relative to a hardware clock counter associated with the clock disciplining software. In one embodiment, the extra hardware can be a sampling logic, which captures a state of a hardware clock counter upon PPS detection. In another embodiment, the extra hardware can initiate a counter that calculates a delay by the clock disciplining software in reading the hardware clock counter. The disciplining software can then subtract the calculated delay from a hardware clock counter to obtain the original PPS signal.

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