中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

93 records (took 0.018 seconds)

    Universal offloading engine
    11.
    发明授权
    Universal offloading engine 有权

    公开(公告)号：US10185678B1

    公开(公告)日：2019-01-22

    申请号：US14954682

    申请日：2015-11-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Gil Stoler ,  Erez Izenberg

    IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

    Abstract: Methods and apparatuses for offloading functionality in an integrated circuit are presented. Certain embodiments are described that disclose methods pertaining to implementation of a universal offload engine that can service several functional blocks, each configured to perform a different function. The offload engine can be iteratively implemented with a common interface to functional blocks. Work descriptors can be used between DMA engines and corresponding functional blocks to instruct the DMA engines how to transport data between memory locations and/or to reformat the data.

    IN-BAND DE-DUPLICATION
    15.
    发明申请
    IN-BAND DE-DUPLICATION 审中-公开

    公开(公告)号：US20170242870A1

    公开(公告)日：2017-08-24

    申请号：US15590898

    申请日：2017-05-09

    Applicant: Amazon Technologies, Inc.

    Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Ron Diamant

    IPC: G06F17/30

    CPC classification number: G06F16/1752 ,  G06F16/27 ,  G06F16/9014

    Abstract: A method for in-band de-duplication, the method may include receiving by a hardware accelerator, a received packet of a first sequence of packets that conveys a first data chunk; applying a data chunk hash calculation process on the received packet while taking into account a hash calculation result obtained when applying the data chunk hash calculation process on a last packet of the first sequence that preceded the received packet; wherein the calculating of the first data chunk hash value is initiated before a completion of a reception of the entire first data chunk by the hardware accelerator.

    Non-coherent and coherent connections in a multi-chip system
    16.
    发明授权
    Non-coherent and coherent connections in a multi-chip system 有权

    公开(公告)号：US11880327B1

    公开(公告)日：2024-01-23

    申请号：US17643132

    申请日：2021-12-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Barak Wasserstrom ,  Yaniv Shapira ,  Erez Izenberg ,  Adi Habusha

    IPC: G06F13/40

    CPC classification number: G06F13/4027

    Abstract: A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

    TRUSTED OR ATTESTED PACKET TIMESTAMPING
    18.
    发明公开
    TRUSTED OR ATTESTED PACKET TIMESTAMPING 审中-公开

    公开(公告)号：US20230308378A1

    公开(公告)日：2023-09-28

    申请号：US17705157

    申请日：2022-03-25

    Applicant: Amazon Technologies, Inc.

    Inventor： Alan Michael Judge ,  Said Bshara ,  Julien Ridoux ,  Joshua Benjamin Levinson ,  David James Goodell ,  Erez Izenberg ,  Anthony Nicholas Liguori

    IPC: H04L43/106 ,  H04L43/0852

    CPC classification number: H04L43/106 ,  H04L43/0852 ,  H04L2212/00

    Abstract: Various embodiments of apparatuses and methods for trusted and/or attested packet timestamping are described. In some embodiments, the disclosed system and methods include a reference timekeeper providing a reference clock to host computing devices. The host computing devices host compute instances using a first set of computing resources, and also contain isolated timing hardware utilizing a different set of computing resources. The isolated timing hardware sets a hardware clock based on a signal corresponding to the reference clock from the reference timekeeper. The isolated timing hardware then receives a packet from a particular compute instance, creates a timestamp for the packet based at least in part on the hardware clock, where the timestamp is outside the control of the compute instances, and sends the packet and the timestamp through a data network to transmit to a packet destination.

    Configurable logic platform
    19.
    发明授权
    Configurable logic platform 有权

    公开(公告)号：US11474966B2

    公开(公告)日：2022-10-18

    申请号：US17184507

    申请日：2021-02-24

    Applicant: Amazon Technologies, Inc.

    Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

    IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Patent Agency Ranking