公开(公告)号：US20160134278A1

公开(公告)日：2016-05-12

申请号：US14534662

申请日：2014-11-06

Applicant: Analog Devices, Inc.

Inventor： Jie Zhou ,  Arthur J. Kalb

IPC: H03K17/687

Abstract: Apparatus and methods for reducing charge injection mismatch are provided herein. In certain implementations, an electronic circuit includes one or more switch banks. Each switch bank can include a selection circuit and a plurality of switches that can be controlled using one or more clock signals. The selection circuit can select a first portion of the switches for operation in a first switch group and a second portion of the switches for operation in a second switch group. During a calibration, the electronic circuit's charge injection mismatch can be directly or indirectly observed for different switch configurations of the switch banks. The electronic circuit can be programmed to operate with the selected switch configurations of the switch banks to provide the electronic circuit with small charge injection mismatch.

Abstract translation: 本文提供了用于减少电荷注入失配的装置和方法。 在某些实施方式中，电子电路包括一个或多个开关组。 每个开关组可以包括可以使用一个或多个时钟信号来控制的选择电路和多个开关。 选择电路可以选择用于在第一开关组中操作的开关的第一部分和用于在第二开关组中操作的开关的第二部分。 在校准期间，可以直接或间接地观察电子电路的电荷注入失配，用于开关组的不同开关配置。 电子电路可以被编程为使用开关组的所选择的开关配置来操作，以为电子电路提供小的电荷注入不匹配。

公开(公告)号：US20130200878A1

公开(公告)日：2013-08-08

申请号：US13757241

申请日：2013-02-01

Applicant: ANALOG DEVICES, INC.

Inventor： Arthur J. Kalb ,  John Sawa Shafran

IPC: G05F3/16

CPC classification number: G05F3/16 ,  G05F3/20 ,  G05F3/30

Abstract: A voltage reference circuit comprises a plurality of ΔVBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ΔVBE voltage. The plurality of ΔVBE cells are stacked such that their ΔVBE voltages are summed. A last stage is coupled to the summed ΔVBE voltages and arranged to generate one or more VBE voltages which are summed with the ΔVBE voltages to provide a reference voltage. This arrangement serves to cancel out first-order noise and mismatch associated with the two current sources present in each ΔVBE cell, such that the voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.

Abstract translation: 一个电压参考电路包括多个DeltaVBE电池，每个都包括四个双极结型晶体管（BJT），它们以交叉四分量配置连接并被布置成产生一个ΔVVV电压。 多个DeltaVBE单元被堆叠，使得它们的DeltaVBE电压相加。 最后一级耦合到总和的ΔVVV电压并被布置成产生一个或多个VBE电压，它们与DeltaVBE电压相加以提供参考电压。 这种布置用于抵消与每个DeltaVBE单元中存在的两个电流源相关联的一阶噪声和失配，使得电压参考电路在带隙电压输出中提供超低的1 / f噪声。

公开(公告)号：US20250158578A1

公开(公告)日：2025-05-15

申请号：US18924349

申请日：2024-10-23

Applicant: Analog Devices, Inc.

Inventor： Arthur J. Kalb ,  Yoshinori Kusuda

IPC: H03F1/52 ,  H02H3/20 ,  H02M1/32

Abstract: Apparatus and methods for amplifier input-overvoltage protection with low leakage current are provided herein. In certain embodiments, amplifier input circuitry for an amplifier includes a pair of input terminals, a pair of input transistors each having a control input (for instance, a transistor gate), a pair of protection transistors each connected between one of the input terminals and the control input of a corresponding one of the input transistors, and a bidirectional clamp connected between the control inputs of the input transistors. Implementing the amplifier input circuitry in this manner provides a number of advantages including, but not limited to, robust protection against input overvoltage and low input-leakage current.

公开(公告)号：US10720919B2

公开(公告)日：2020-07-21

申请号：US14534662

申请日：2014-11-06

Applicant: Analog Devices, Inc.

Inventor： Jie Zhou ,  Arthur J. Kalb

IPC: H03K17/687 ,  H03K19/0185

Abstract: Apparatus and methods for reducing charge injection mismatch are provided herein. In certain implementations, an electronic circuit includes one or more switch banks. Each switch bank can include a selection circuit and a plurality of switches that can be controlled using one or more clock signals. The selection circuit can select a first portion of the switches for operation in a first switch group and a second portion of the switches for operation in a second switch group. During a calibration, the electronic circuit's charge injection mismatch can be directly or indirectly observed for different switch configurations of the switch banks. The electronic circuit can be programmed to operate with the selected switch configurations of the switch banks to provide the electronic circuit with small charge injection mismatch.

公开(公告)号：US10327659B2

公开(公告)日：2019-06-25

申请号：US15621621

申请日：2017-06-13

Applicant: Analog Devices, Inc.

Inventor： Arthur J. Kalb ,  Yogesh Jayaraman Sharma ,  Marvin Liu Shu

IPC: A61B5/00 ,  A61B5/0428 ,  A61B5/0452 ,  H03M3/00 ,  H03M1/06 ,  H03M1/18 ,  H03M1/68

Abstract: An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.

公开(公告)号：US09285820B2

公开(公告)日：2016-03-15

申请号：US13757241

申请日：2013-02-01

Applicant: ANALOG DEVICES, INC.

Inventor： Arthur J. Kalb ,  John Sawa Shafran

IPC: G05F3/16 ,  G05F3/20 ,  G05F3/30

CPC classification number: G05F3/16 ,  G05F3/20 ,  G05F3/30

Abstract: A voltage reference circuit comprises a plurality of ΔVBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ΔVBE voltage. The plurality of ΔVBE cells are stacked such that their ΔVBE voltages are summed. A last stage is coupled to the summed ΔVBE voltages and arranged to generate one or more VBE voltages which are summed with the ΔVBE voltages to provide a reference voltage. This arrangement serves to cancel out first-order noise and mismatch associated with the two current sources present in each ΔVBE cell, such that the voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.

Abstract translation: 一个电压参考电路包括多个＆Dgr; VBE单元，每个单元包括四个双极结型晶体管（BJT），它们以交叉 - 四边形配置连接并被布置成产生＆Dgr; VBE电压。 堆叠多个＆Dgr; VBE单元，使得它们的＆Dgr; VBE电压相加。 最后阶段耦合到总和的Dgr; VBE电压，并被布置成产生一个或多个VBE电压，其与Dgr; VBE电压相加以提供参考电压。 这种布置用于消除与每个＆Dgr; VBE单元中存在的两个电流源相关联的一阶噪声和失配，使得该参考电压在带隙电压输出中提供超低的1 / f噪声。

公开(公告)号：US20150054576A1

公开(公告)日：2015-02-26

申请号：US14334569

申请日：2014-07-17

Applicant: Analog Devices, Inc.

Inventor： Jie Zhou ,  Arthur J. Kalb ,  Mark D. Reisiger

IPC: H03F3/393 ,  H03F3/45

CPC classification number: H03F3/393 ,  H03F3/45192 ,  H03F3/45775 ,  H03F2200/271 ,  H03F2203/45048

Abstract: Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation. The chopper amplifier can be programmed to operate with the selected transistor configurations of the differential transistor banks to provide the amplifier with low input offset.

Abstract translation: 本文提供了斩波放大器的装置和方法。 在某些配置中，斩波放大器包括至少一个包括选择电路和多个晶体管的差分晶体管组。 选择电路可以选择用于在第一晶体管组中操作的晶体管的第一部分和用于在第二晶体管组中操作的晶体管的第二部分。 在校准期间，可以对差分晶体管组的不同晶体管配置观察到斩波放大器的输入偏移。 尽管特定存储体的晶体管可被设计成具有大致相同的驱动强度和/或几何形状，但是由于晶体管之间的制造失配（例如工艺变化），斩波放大器可以在不同的晶体管配置中具有不同的输入偏移。 斩波放大器可以编程为与差分晶体管组的选定晶体管配置一起工作，为放大器提供低输入偏移。

公开(公告)号：US08930874B2

公开(公告)日：2015-01-06

申请号：US13711038

申请日：2012-12-11

Applicant: Analog Devices, Inc.

Inventor： Matthew N. Duff ,  Arthur J. Kalb

IPC: G06F17/50 ,  H03H11/12

CPC classification number: G06F17/5063 ,  H03H11/1221 ,  H03H11/1265 ,  H03H11/1286

Abstract: A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately.

Abstract translation: 提供了根据滤波器设计工具的实施例的方法，并且包括通过用户接口接收用于模拟滤波器的滤波器参数，其中滤波器参数包括与模拟滤波器的应用需求相关的优化参数， 优化参数，基于优化过滤器计算设计输出，并在用户界面上显示设计输出。 该方法还可以包括接收指定要显示的设计输出的观看参数。 在各种实施例中，用户界面包括输入区域，观看区域和一个或多个页面中的窗口区域，其中输入区域与至少一个页面中的观看区域相邻。 过滤器参数可以输入到输入区域，并且设计输出被计算并基本上立即显示在连续的观察区域中。

公开(公告)号：US20140077862A1

公开(公告)日：2014-03-20

申请号：US14084050

申请日：2013-11-19

Applicant: ANALOG DEVICES, INC.

Inventor： Arthur J. Kalb ,  Evaldo M. Miranda

IPC: H03K17/56

CPC classification number: H03K17/56 ,  H03H7/40 ,  H03H11/28

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract translation: 基于认识到制造变化引入旨在相同的电子子网络的轻微差异，形成电网络以产生至少一个期望的性能特征的近似。 通过提供一个子网络池，然后选择性地连接这些子网络的特定组合来实现近似所期望的性能特征的网络，这些制造差异变得有利。 子网络类似（例如，电阻器）并且具有相似的测量。