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11.发明申请Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage 失效用于Xdsl多标准输入级的Sigma-Delta模拟数字转换器公开(公告)号：US20080297385A1
公开(公告)日：2008-12-04
申请号：US11661627
申请日：2004-09-02
IPC分类号： H03M3/04
摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.
摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。
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公开(公告)号：US06989778B2
公开(公告)日：2006-01-24
申请号：US10938741
申请日：2004-09-10
IPC分类号： H03M3/00
摘要： A semi-conductor circuit arrangement for a continuous time sigma delta modulator for adding analog input signals to a digital fed back signal and for quantizing the totalled signal comprises a voltage to current conversion circuit (10), an adding circuit (20) with a resistor ladder, a quantizing circuit (40) with comparator elements (45) and a digital to analog conversion circuit (30). For each comparator element (45) its respective input signal is formed by a voltage which is released between a tap in front of a corresponding tapping resistor (22) in a first string of the resistor ladder and a tap in front of a corresponding tapping resistor (22) in a second string of the resistor ladder.
摘要翻译： 一种用于将模拟输入信号加到数字反馈信号并用于量化总计信号的连续时间Σ-Δ调制器的半导体电路装置包括电压 - 电流转换电路（10），具有电阻的加法电路（20） 梯形图，具有比较器元件（45）和数模转换电路（30）的量化电路（40）。 对于每个比较器元件（45），其相应的输入信号由在电阻梯的第一串中的对应的分接电阻器（22）前面的抽头和相应的分接电阻器前面的抽头之间的抽头释放的电压形成 （22）在电阻梯的第二串中。
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13.发明授权Sigma-delta analog-digital converter for an xDSL multistandard input stage 失效用于xDSL多标准输入级的Sigma-delta模数转换器公开(公告)号：US07576670B2
公开(公告)日：2009-08-18
申请号：US11661627
申请日：2004-09-02
IPC分类号： H03M3/00
摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.
摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。
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公开(公告)号：US20050128115A1
公开(公告)日：2005-06-16
申请号：US10774311
申请日：2004-02-06
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03H11/1217 , H03H11/126 , H03H11/1286 , H03M3/43 , H03M3/454
摘要： A loop filter for a continuous time sigma delta analog to digital converter which converts an analog input signal into a digital output signal, said loop filter comprising an active analog filter which includes active devices for providing a power gain, wherein the number of active devices is lower than the filter order of said active analog filter.
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公开(公告)号：US20050093732A1
公开(公告)日：2005-05-05
申请号：US10938741
申请日：2004-09-10
摘要： A semi-conductor circuit arrangement for a continuous time sigma delta modulator for adding analog input signals to a digital fed back signal and for quantizing the totalled signal comprises a voltage to current conversion circuit (10), an adding circuit (20) with a resistor ladder, a quantizing circuit (40) with comparator elements (45) and a digital to analog conversion circuit (30). For each comparator element (45) its respective input signal is formed by a voltage which is released between a tap in front of a corresponding tapping resistor (22) in a first string of the resistor ladder and a tap in front of a corresponding tapping resistor (22) in a second string of the resistor ladder.
摘要翻译： 一种用于将模拟输入信号加到数字反馈信号并用于量化总计信号的连续时间Σ-Δ调制器的半导体电路装置包括电压 - 电流转换电路（10），具有电阻的加法电路（20） 梯形图，具有比较器元件（45）和数模转换电路（30）的量化电路（40）。 对于每个比较器元件（45），其相应的输入信号由在电阻梯的第一串中的对应的分接电阻器（22）前面的抽头和相应的分接电阻器前面的抽头之间的抽头释放的电压形成 （22）在电阻梯的第二串中。
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公开(公告)号：US20100134190A1
公开(公告)日：2010-06-03
申请号：US12327739
申请日：2008-12-03
申请人： Fabio Ballarin , Alfonso D'Andretta , Martin Clara , Antonio Di Giandomenico , Dario Giotta , Andreas Wiesbauer
发明人： Fabio Ballarin , Alfonso D'Andretta , Martin Clara , Antonio Di Giandomenico , Dario Giotta , Andreas Wiesbauer
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45528
摘要： Systems and methods for implementing a programmable network for a multimode conditionally stable operational amplifier are disclosed.
摘要翻译： 公开了用于实现用于多模有条件稳定的运算放大器的可编程网络的系统和方法。
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17.发明授权公开(公告)号：US06967606B2
公开(公告)日：2005-11-22
申请号：US10774311
申请日：2004-02-06
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03H11/1217 , H03H11/126 , H03H11/1286 , H03M3/43 , H03M3/454
摘要： A loop filter for a continuous time sigma delta analog to digital converter which converts an analog input signal into a digital output signal, said loop filter comprising an active analog filter which includes active devices for providing a power gain, wherein the number of active devices is lower than the filter order of said active analog filter.
摘要翻译： 一种用于将模拟输入信号转换为数字输出信号的连续时间Σ-Δ模数转换器的环路滤波器，所述环路滤波器包括有源模拟滤波器，其包括用于提供功率增益的有源器件，其中有源器件数目为 低于所述有源模拟滤波器的滤波器顺序。
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18.发明申请Method for digital/ analog conversion and corresponding digital/ analog converter device 有权数字/模拟转换方法及相应的数/模转换器装置公开(公告)号：US20050116851A1
公开(公告)日：2005-06-02
申请号：US10971570
申请日：2004-10-22
CPC分类号： H03M1/0678 , H03M1/0665 , H03M1/747 , H03M3/464
摘要： Method for digital/analog conversion and corresponding digital/analog converter device A method and a device for digital/analog conversion are proposed, whereby for improved use of a “dynamic element matching” algorithm, in particular a “data weighted averaging” algorithm, the number of existing conversion elements is greater than a maximum number of possible input or control codes for the conversion elements (7), that is to say greater than a number of conversion elements, which would actually be necessary for a maximum value of the digital word to be converted in each case.
摘要翻译： 数字/模拟转换方法和相应的数/模转换器装置提出了一种用于数/模转换的方法和装置，为了改进使用“动态元件匹配”算法，特别是“数据加权平均”算法， 现有转换元件的数量大于转换元件（7）的可能的输入或控制代码的最大数量，也就是说大于转换元件的数量，这对于数字字的最大值实际上是必需的 在每种情况下进行转换。
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19.发明授权Method for digital/analog conversion and corresponding digital/analog converter device 有权数字/模拟转换方法及相应的数/模转换器装置公开(公告)号：US07199741B2
公开(公告)日：2007-04-03
申请号：US10971570
申请日：2004-10-22
IPC分类号： H03M1/66
CPC分类号： H03M1/0678 , H03M1/0665 , H03M1/747 , H03M3/464
摘要： A method and a device for digital/analog conversion are proposed, whereby for improved use of a “dynamic element matching” algorithm, in particular a “data weighted averaging” algorithm, the number of existing conversion elements is greater than a maximum number of possible input or control codes for the conversion elements (7), that is to say greater than a number of conversion elements, which would actually be necessary for a maximum value of the digital word to be converted in each case.
摘要翻译： 提出了一种用于数字/模拟转换的方法和装置，其中为了改进使用“动态元件匹配”算法，特别是“数据加权平均”算法，现有转换元件的数量大于可能的最大数量 用于转换元件（7）的输入或控制代码，也就是说大于转换元件的数量，这在每种情况下实际上对于要转换的数字字的最大值是必需的。
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公开(公告)号：US07327193B2
公开(公告)日：2008-02-05
申请号：US11230284
申请日：2005-09-19
IPC分类号： H03F3/45
CPC分类号： H03F1/34 , H03F3/45085 , H03F3/45475 , H03F3/45659 , H03F2203/45726
摘要： An amplifier and method of setting the amplifier is presented. The amplifier is set by setting a mean value between voltage values at first and second outputs of the amplifier. The mean value is pulled towards a certain voltage potential. A circuit node is coupled to the first and to the second output. The circuit node is connected, via at least one resistor and a respective switch, to the certain voltage potential assigned to the respective resistor.
摘要翻译： 提出了放大器和放大器设置方法。 通过设置放大器的第一和第二输出端的电压值之间的平均值来设置放大器。 平均值被拉向某一电压电位。 电路节点耦合到第一和第二输出端。 电路节点经由至少一个电阻器和相应的开关连接到分配给相应电阻器的一定电压电位。
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