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公开(公告)号：US20150348600A1
公开(公告)日：2015-12-03
申请号：US14291582
申请日：2014-05-30
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia , Anshul Y. Mehta , Amrinder S. Barn , Greg M. Hess
CPC classification number: G11C5/147 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/4402
Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.
Abstract translation: 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。
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公开(公告)号：US20150207462A1
公开(公告)日：2015-07-23
申请号：US14158231
申请日：2014-01-17
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia , Amrinder S. Barn
CPC classification number: G11C7/1051 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/1048
Abstract: A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.
Abstract translation: 提出了一种用于比较一对输入信号的电压电平的装置。 该器件可以包括前置放大器电路和差分放大器。 前置放大器电路可以被配置为接收第一输入信号和第二输入信号，调整该对输入信号中的每一个的电压电平，并且在从所述输入信号的断言之后的预定时间段之后断言控制信号 一个使能信号。 差分放大器可以被配置为响应于控制信号的断言，放大第一输入信号和第二输入信号之间的电压差，这取决于一对输入信号的调整的电压电平。
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公开(公告)号：US10261563B1
公开(公告)日：2019-04-16
申请号：US15839317
申请日：2017-12-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Kumar Bhatia
IPC: H03K17/16 , G06F1/3206 , G06F17/50 , H03K17/62 , H03K17/22
Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.
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公开(公告)号：US10033356B2
公开(公告)日：2018-07-24
申请号：US15355109
申请日：2016-11-18
Applicant: Apple Inc.
Inventor： Zhao Wang , Sheela R. Shreedharan , Ajay Kumar Bhatia , Michael R. Seningen
IPC: H03K3/012 , H03K3/3562
Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.
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公开(公告)号：US20160191031A1
公开(公告)日：2016-06-30
申请号：US15065952
申请日：2016-03-10
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia
CPC classification number: H03K5/134 , G01R19/0084 , G01R31/40 , G06F1/08 , G06F1/24 , G06F1/26 , G06F1/305 , G11C5/14 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C2207/2281 , G11C2207/229 , H03K5/13 , H03K5/133 , H03K19/00369 , H03K2005/00019 , H03K2005/00039
Abstract: Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed.
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Patent Agency Ranking
公开(公告)号：US09350326B2
公开(公告)日：2016-05-24
申请号：US14455195
申请日：2014-08-08
Applicant: Apple Inc.
Inventor： Bo Tang , Ajay Kumar Bhatia
IPC: H03K3/012
CPC classification number: H03K3/012 , H03K5/24 , H03K5/249 , H03K19/0013
Abstract: A apparatus including a clock source and a comparison circuit is presented. The clock source may be configured to generate a clock signal. The comparison circuit may be configured select a first frequency of the clock signal and to receive a plurality of voltage signal inputs for comparison. The comparison circuit may be further configured to compare a voltage level of a first voltage signal input of the plurality of voltage signal inputs to a voltage level of a second voltage signal input of the plurality of voltage signal inputs responsive to an active edge of the clock signal. The comparison circuit may also be configured to determine a comparison value corresponding to the comparison of the voltage levels and to select a second frequency of the clock signal dependent upon the comparison value, in which the second frequency is different than the first frequency.
Abstract translation: 提出了一种包括时钟源和比较电路的装置。 时钟源可以被配置为产生时钟信号。 比较电路可以被配置为选择时钟信号的第一频率并且接收多个电压信号输入用于比较。 比较电路还可以被配置为将响应于时钟的有效边沿将多个电压信号输入的第一电压信号输入的电压电平与多个电压信号输入的第二电压信号输入的电压电平进行比较 信号。 比较电路还可以被配置为确定对应于电压电平的比较的比较值，并且根据比较值选择时钟信号的第二频率，其中第二频率不同于第一频率。
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公开(公告)号：US09324386B2
公开(公告)日：2016-04-26
申请号：US14158231
申请日：2014-01-17
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia , Amrinder S Barn
CPC classification number: G11C7/1051 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/1048
Abstract: A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.
Abstract translation: 提出了一种用于比较一对输入信号的电压电平的装置。 该器件可以包括前置放大器电路和差分放大器。 前置放大器电路可以被配置为接收第一输入信号和第二输入信号，调整该对输入信号中的每一个的电压电平，并且在从所述输入信号的断言之后的预定时间段之后断言控制信号 一个使能信号。 差分放大器可以被配置为响应于控制信号的断言，放大第一输入信号和第二输入信号之间的电压差，这取决于一对输入信号的调整的电压电平。
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公开(公告)号：US20160055889A1
公开(公告)日：2016-02-25
申请号：US14467376
申请日：2014-08-25
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia , Aravind Kandala
CPC classification number: G11C7/222 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/419 , G11C2207/2254 , G11C2207/229
Abstract: Embodiments that may allow for selectively tuning a delay of individual write paths within a memory are disclosed. The memory may comprise a memory array, a first data latch, a second data latch, and circuitry. The first and second data latches may be configured to each sample a respective data value, responsive to detecting a first edge of a first clock signal. The circuitry may be configured to detect the first edge of the first clock signal, and select an output of the first data latch responsive to detecting the first edge of the first clock signal. The circuitry may detect a subsequent opposite edge of the first clock signal, and select an output of the second data latch responsive to sampling the opposite edge of the first clock signal.
Abstract translation: 公开了可以允许选择性地调整存储器内的各个写入路径的延迟的实施例。 存储器可以包括存储器阵列，第一数据锁存器，第二数据锁存器和电路。 响应于检测到第一时钟信号的第一边缘，第一和第二数据锁存器可以被配置为对各自的数据值进行采样。 电路可以被配置为检测第一时钟信号的第一边缘，并且响应于检测到第一时钟信号的第一边缘而选择第一数据锁存器的输出。 电路可以检测第一时钟信号的后续相对边缘，并且响应于对第一时钟信号的相对边缘采样来选择第二数据锁存器的输出。
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公开(公告)号：US20160043707A1
公开(公告)日：2016-02-11
申请号：US14451721
申请日：2014-08-05
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia
CPC classification number: H03K5/134 , G01R19/0084 , G01R31/40 , G06F1/08 , G06F1/24 , G06F1/26 , G06F1/305 , G11C5/14 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C2207/2281 , G11C2207/229 , H03K5/13 , H03K5/133 , H03K19/00369 , H03K2005/00019 , H03K2005/00039
Abstract: Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed.
Abstract translation: 公开了可以允许选择性地调整定制电路或存储器内的各个逻辑路径的延迟的方法的实施例。 电路可以被配置为监视耦合到定制电路或存储器的电源的电压电平。 响应于电源的电压电平已经改变的确定，可以改变定制电路或存储器内的延迟单元的延迟量。
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公开(公告)号：US08791743B1
公开(公告)日：2014-07-29
申请号：US13769406
申请日：2013-02-18
Applicant: Apple Inc.
Inventor： Bo Tang , Huaimin Li , Ajay Kumar Bhatia
IPC: H03L5/00
CPC classification number: H03K5/003 , H03K3/356104
Abstract: Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.
Abstract translation: 公开了一种装置的实施例，其可以允许将信号从一个功率域转换到另一个功率域，并且在宽的工作范围内具有良好平衡的上升和下降时间。 该装置可以包括输入缓冲器，电压移位电路和输出电路以及输出驱动器。 输入缓冲器可以被配置为在第一电压电平下产生缓冲版本和外部信号的延迟反相版本。 电压移位电路可以被配置为根据输入缓冲器的输出信号产生处于第二电压电平的两个内部信号。 输出电路可以被配置为根据电压移位电路的输出信号产生处于第二电压电平的两个输出驱动器信号。 输出驱动器电路可以被配置为根据两个输出驱动器信号产生处于第二电压电平的输出信号。
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