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11.发明授权公开(公告)号：US12229557B2
公开(公告)日：2025-02-18
申请号：US18601640
申请日：2024-03-11
Applicant: Apple Inc.
Inventor： Brian R. Mestan , Gideon N. Levinsky , Michael L. Karm
Abstract: In an embodiment, a processor comprises an atomic predictor circuit to predict whether or not an atomic operation will complete successfully. The prediction may be used when a subsequent load operation to the same memory location as the atomic operation is executed, to determine whether or not to forward store data from the atomic operation to the subsequent load operation. If the prediction is successful, the store data may be forwarded. If the prediction is unsuccessful, the store data may not be forwarded. In cases where an atomic operation has been failing (not successfully performing the store operation), the prediction may prevent the forwarding of the store data and thus may prevent a subsequent flush of the load.
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12.发明公开公开(公告)号：US20240248717A1
公开(公告)日：2024-07-25
申请号：US18601640
申请日：2024-03-11
Applicant: Apple Inc.
Inventor： Brian R. Mestan , Gideon N. Levinsky , Michael L. Karm
CPC classification number: G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/321 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/528 , G06F2209/521
Abstract: In an embodiment, a processor comprises an atomic predictor circuit to predict whether or not an atomic operation will complete successfully. The prediction may be used when a subsequent load operation to the same memory location as the atomic operation is executed, to determine whether or not to forward store data from the atomic operation to the subsequent load operation. If the prediction is successful, the store data may be forwarded. If the prediction is unsuccessful, the store data may not be forwarded. In cases where an atomic operation has been failing (not successfully performing the store operation), the prediction may prevent the forwarding of the store data and thus may prevent a subsequent flush of the load.
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公开(公告)号：US12007920B2
公开(公告)日：2024-06-11
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20230333851A1
公开(公告)日：2023-10-19
申请号：US18336704
申请日：2023-06-16
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/02 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30087 , G06F9/30043 , G06F12/0238 , G06F12/0875 , G06F9/30047 , G06F9/3834 , G06F9/30101
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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Patent Agency Ranking
公开(公告)号：US20230251985A1
公开(公告)日：2023-08-10
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11720360B2
公开(公告)日：2023-08-08
申请号：US17469504
申请日：2021-09-08
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/02 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30087 , G06F9/30043 , G06F9/30047 , G06F9/30101 , G06F9/3834 , G06F12/0238 , G06F12/0875
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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公开(公告)号：US11630789B2
公开(公告)日：2023-04-18
申请号：US17246311
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11099990B2
公开(公告)日：2021-08-24
申请号：US16545521
申请日：2019-08-20
Applicant: Apple Inc.
Inventor： Gideon N. Levinsky , Brian R. Mestan , Deepak Limaye , Mridul Agarwal
IPC: G06F12/0811
Abstract: A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.
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公开(公告)号：US20210056024A1
公开(公告)日：2021-02-25
申请号：US16545521
申请日：2019-08-20
Applicant: Apple Inc.
Inventor： Gideon N. Levinsky , Brian R. Mestan , Deepak Limaye , Mridul Agarwal
IPC: G06F12/0811
Abstract: A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.
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