公开(公告)号：US20210201987A1

公开(公告)日：2021-07-01

申请号：US17182341

申请日：2021-02-23

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US20210020231A1

公开(公告)日：2021-01-21

申请号：US16515351

申请日：2019-07-18

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US20150235634A1

公开(公告)日：2015-08-20

申请号：US14183321

申请日：2014-02-18

Applicant: Apple Inc.

Inventor： Michael L. Liu ,  Liang Deng

IPC: G09G5/395 ,  H03K19/173 ,  H03K19/00

CPC classification number: G09G5/395 ,  G06F7/533 ,  H03K19/0013 ,  H03K19/1737

Abstract: Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.

Abstract translation: 公开了涉及不对称电路的技术。 在一些实施例中，存储元件被配置为在时间间隔期间将第一输入值保持为非对称电路的输入。 例如，在一个实施例中，时间间隔可以对应于视频数据的帧，并且存储元件可以被配置为存储用于视频数据帧的滤波器系数。 在一些实施例中，存储元件可以被配置为将该值存储为用于由非对称电路进行的多个操作的常数。 在一些实施例中，非对称电路被配置为基于第一输入值和一组第二输入值中的相应值来产生多个输出值。 在一些实施例中，非对称电路是泄漏功率不对称和/或关键路径不对称。 这可能会提高性能和/或降低功耗。

公开(公告)号：US20180074743A1

公开(公告)日：2018-03-15

申请号：US15263833

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC: G06F3/06 ,  G06F1/08

CPC classification number: G06F3/0634 ,  G06F1/08 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/1689 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US09607586B2

公开(公告)日：2017-03-28

申请号：US14183321

申请日：2014-02-18

Applicant: Apple Inc.

Inventor： Michael L. Liu ,  Liang Deng

IPC: G09G5/395 ,  H03K19/00 ,  G06F7/533 ,  H03K19/173

CPC classification number: G09G5/395 ,  G06F7/533 ,  H03K19/0013 ,  H03K19/1737

Abstract: Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.