公开(公告)号：US11093249B2

公开(公告)日：2021-08-17

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206 ,  G06F12/0875

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US10990159B2

公开(公告)日：2021-04-27

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F9/38 ,  G06F3/06 ,  G06F1/3287 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

公开(公告)号：US10410688B2

公开(公告)日：2019-09-10

申请号：US16208101

申请日：2018-12-03

Applicant: Apple Inc.

Inventor： Shih-Chieh Wen ,  Jong-Suk Lee ,  Ramesh B. Gunna

IPC: G06F12/08 ,  G11C5/14 ,  G06F1/26 ,  G06F9/28 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/20 ,  G06F1/30 ,  G06F9/00 ,  G06F1/00

Abstract: An IC in which a power state of a circuit in one power domain is managed based at least in part on a power state of a circuit in another power domain is disclosed. In one embodiment, an IC includes first and second functional circuit blocks in first and second power domains, respectively. A third functional block shared by the first and second is also implemented in the first power domain. A power management unit may control power states of each of the first, second, and third functional circuit blocks. The power management circuit may, when the first functional circuit block is in a sleep state, set a power state of the third functional block in accordance with that of the second functional circuit block.

公开(公告)号：US20190221241A1

公开(公告)日：2019-07-18

申请号：US16208101

申请日：2018-12-03

Applicant: Apple Inc.

Inventor： Shih-Chieh Wen ,  Jong-Suk Lee ,  Ramesh B. Gunna

IPC: G11C5/14 ,  G06F1/26 ,  G06F9/28 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/30 ,  G06F11/30 ,  G06F11/20

CPC classification number: G11C5/141 ,  G06F1/00 ,  G06F1/26 ,  G06F1/30 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/00 ,  G06F9/28 ,  G06F11/2015 ,  G06F11/3058 ,  G11C5/148

Abstract: An IC in which a power state of a circuit in one power domain is managed based at least in part on a power state of a circuit in another power domain is disclosed. In one embodiment, an IC includes first and second functional circuit blocks in first and second power domains, respectively. A third functional block shared by the first and second is also implemented in the first power domain. A power management unit may control power states of each of the first, second, and third functional circuit blocks. The power management circuit may, when the first functional circuit block is in a sleep state, set a power state of the third functional block in accordance with that of the second functional circuit block.

公开(公告)号：US20190196834A1

公开(公告)日：2019-06-27

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30058 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US20190086942A1

公开(公告)日：2019-03-21

申请号：US15708229

申请日：2017-09-19

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Ramesh B. Gunna ,  Shih-Chieh Wen

IPC: G05F1/46 ,  H03K5/04

CPC classification number: G05F1/46 ,  G06F1/26 ,  H03K5/04 ,  H03K19/00346

Abstract: A method and apparatus for reducing capacitor noise in electronic systems is disclosed. A system includes at least one functional circuit block coupled to receive a variable supply voltage. The value of the supply voltage is controlled by a power management circuit. Changing a performance state of the functional circuit block includes increasing the supply voltage for higher performance, and reducing the supply voltage for reduced performance demands. The power management circuit, in changing to a higher performance state, increases the supply voltage at a first rate. A rate control circuit causes the power management circuit to reduce the supply voltage, when changing to a lower performance state, at a second rate that is less than the first rate.