公开(公告)号：US11211111B1

公开(公告)日：2021-12-28

申请号：US17038795

申请日：2020-09-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Supreet Jeloka ,  Andy Wangkun Chen

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/4094 ,  G11C5/02 ,  G11C15/04 ,  G11C11/4097

Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.

公开(公告)号：US20210295898A1

公开(公告)日：2021-09-23

申请号：US16824663

申请日：2020-03-19

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Ettore Amirante

IPC: G11C11/4097 ,  G11C11/4094 ,  G11C11/408 ,  G11C5/02

Abstract: Various implementations described herein are related to a device having a bitcell. The device may include horizontal bitlines coupled to the bitcell. The horizontal bitlines may include multiple first read bitlines disposed in a horizontal direction with respect to the bitcell. The device may include vertical bitlines coupled to the bitcell. The vertical bitlines may include multiple second read bitlines disposed in a vertical direction with respect to the bitcell.

公开(公告)号：US11011222B2

公开(公告)日：2021-05-18

申请号：US16294577

申请日：2019-03-06

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

公开(公告)号：US20200136643A1

公开(公告)日：2020-04-30

申请号：US16170723

申请日：2018-10-25

Applicant: Arm Limited

Inventor： Shardendu Shekhar ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: H03M7/00 ,  H03K19/20 ,  H03K19/21 ,  H03K19/0944 ,  H03M7/30

Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

公开(公告)号：US20190244656A1

公开(公告)日：2019-08-08

申请号：US15891212

申请日：2018-02-07

Applicant: Arm Limited

Inventor： Yicong Li ,  Andy Wangkun Chen ,  Sharryl Renee Dettmer ,  Lalit Gupta ,  Jitendra Dasani ,  Yeon Jun Park ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/4097 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

公开(公告)号：US10083269B2

公开(公告)日：2018-09-25

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul De Dood ,  Marlin Wayne Frederick ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

公开(公告)号：US20250140310A1

公开(公告)日：2025-05-01

申请号：US18495834

申请日：2023-10-27

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Andy Wangkun Chen ,  Ettore Amirante ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412

Abstract: Various implementations described herein are directed to a device having an array of bitcells with a first bitcell disposed adjacent to a second bitcell. The device may have a first wordline coupled to first transistors in the first bitcell, and the device may have a second wordline coupled to second transistors in the second bitcell. Also, the device may have a buried ground line coupled to the first transistors and the second transistors.

公开(公告)号：US20250087251A1

公开(公告)日：2025-03-13

申请号：US18367902

申请日：2023-09-13

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C5/14

Abstract: Various implementations described herein are directed to a device having a power-gate structure with multiple transistors including a first transistor and a second transistor. The first transistor may be coupled between a first voltage node and a second voltage node, and the second transistor may be coupled between the second voltage node and a third voltage node that is coupled to the second voltage node.

公开(公告)号：US20250015133A1

公开(公告)日：2025-01-09

申请号：US18219292

申请日：2023-07-07

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Dileep Choorakuzhi Ramakrishnan ,  Subramanya Ravindra Shindagikar ,  Ala Srinivasa Rao

IPC: H01L29/06 ,  G06F30/392 ,  H01L27/092 ,  H01L29/78

Abstract: Various implementations described herein are directed to a device having a skew cell architecture with multiple diffusion regions including P-type diffusion regions disposed between N-type diffusion regions. The device may have power rails including a voltage supply rail disposed between ground rails. The device may have poly-gate rails disposed between the ground rails. The poly-gate rails may be cut to provide an open space between at least one N-type diffusion region and at least one P-type diffusion region.

公开(公告)号：US20240153551A1

公开(公告)日：2024-05-09

申请号：US17980335

申请日：2022-11-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Vivek Asthana ,  Sony ,  Ettore Amirante ,  Yew Keong Chong

IPC: G11C11/418

CPC classification number: G11C11/418

Abstract: Various implementations described herein are related to a device having multi-page memory with a first core array and bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines. The device may have wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines. The device may have buried metal lines formed within a substrate, and the buried metal lines may be used to couple the wordline drivers to the first wordlines.