公开(公告)号：US20240095183A1

公开(公告)日：2024-03-21

申请号：US18263665

申请日：2022-02-02

Applicant: Arm Limited

Inventor： Carlos Garcia-Tobin ,  Bruce James Mathewson ,  Matthew Lucien Evans ,  Richard Roy Grisenthwaite

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027

Abstract: An apparatus and method are provided for storing a plurality of translation entries in a cache, each translation entry corresponding to one of a plurality of page table entries and defining a translation between a first address and a second address, and encoding control information indicative of an attribute of each page table entry; returning, in response to a lookup querying a first lookup address, a corresponding second address when the first lookup address corresponds to one of the plurality of translation entries stored in the cache; modifying at least some of the control information in response to notification of a modification of the attribute in a page table entry; and retaining in the cache at least one translation entry corresponding to the page table entry for use in a subsequent address lookup querying a corresponding first lookup address in response to the notification of the modification of the attribute in the page table entry.

公开(公告)号：US11599467B2

公开(公告)日：2023-03-07

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

公开(公告)号：US20220382679A1

公开(公告)日：2022-12-01

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

公开(公告)号：US11263137B2

公开(公告)日：2022-03-01

申请号：US16884359

申请日：2020-05-27

Applicant: Arm Limited

Inventor： Jose Alberto Joao ,  Tiago Rogerio Muck ,  Joshua Randall ,  Alejandro Rico Carro ,  Bruce James Mathewson

IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0875

Abstract: A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.

公开(公告)号：US10970225B1

公开(公告)日：2021-04-06

申请号：US16591827

申请日：2019-10-03

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC: G06F12/0897 ,  G06F12/0868 ,  G06F12/0871 ,  G06F3/06

Abstract: An apparatus and method are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element may be arranged to issue a cache maintenance operation request specifying a memory address range in order to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements. The given requester element may be arranged to detect when there is a need to issue a write request prior to the cache maintenance operation request in order to cause a write operation to be performed in respect of data within the specified memory address range, and in that event to generate a combined write and cache maintenance operation request to be issued instead of the write request and a subsequent cache maintenance operation request. A recipient completer element that receives the combined write and cache maintenance operation request may then be arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. This can significantly reduce latency in the handling of cache maintenance operations, and can provide for reduced bandwidth utilisation.

公开(公告)号：US10324858B2

公开(公告)日：2019-06-18

申请号：US15620017

申请日：2017-06-12

Applicant: ARM LIMITED

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Matthew Lucien Evans ,  Paul Gilbert Meyer ,  Andrew Brookfield Swaine

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

公开(公告)号：US10223002B2

公开(公告)日：2019-03-05

申请号：US15427335

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Geoffray Matthieu Lacourba

IPC: G06F3/06 ,  G06F12/06 ,  G06F9/52

Abstract: A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. The compare data value is packed into a first region of the data field in dependence of an offset portion of the target address and having a position within the data field corresponding to the position of the target data value within the storage location. This reduces latency and circuitry required at the processing unit for handling the compare and swap transaction.

公开(公告)号：US09477623B2

公开(公告)日：2016-10-25

申请号：US13960128

申请日：2013-08-06

Applicant: ARM LIMITED

Inventor： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

公开(公告)号：US11314675B2

公开(公告)日：2022-04-26

申请号：US16659762

申请日：2019-10-22

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune ,  Daniel Adam Sara ,  Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F12/0888 ,  G06F12/0815

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

公开(公告)号：US20210374059A1

公开(公告)日：2021-12-02

申请号：US16884359

申请日：2020-05-27

Applicant: Arm Limited

Inventor： Jose Alberto Joao ,  Tiago Rogerio Muck ,  Joshua Randall ,  Alejandro Rico Carro ,  Bruce James Mathewson

IPC: G06F12/0842 ,  G06F12/0875

Abstract: A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.