公开(公告)号：US10223002B2

公开(公告)日：2019-03-05

申请号：US15427335

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Geoffray Matthieu Lacourba

IPC: G06F3/06 ,  G06F12/06 ,  G06F9/52

Abstract: A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. The compare data value is packed into a first region of the data field in dependence of an offset portion of the target address and having a position within the data field corresponding to the position of the target data value within the storage location. This reduces latency and circuitry required at the processing unit for handling the compare and swap transaction.

公开(公告)号：US10042766B1

公开(公告)日：2018-08-07

申请号：US15422691

申请日：2017-02-02

Applicant: ARM Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Phanindra Kumar Mannava

IPC: G06F13/00 ,  G06F12/0831 ,  G06F15/78 ,  G06F12/0868 ,  G06F13/42 ,  G06F13/16 ,  G06F12/06 ,  G06F13/38

Abstract: A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.

公开(公告)号：US11256623B2

公开(公告)日：2022-02-22

申请号：US15427459

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Michael Filippo ,  Paul Gilbert Meyer ,  Alex James Waugh ,  Geoffray Matthieu Lacourba

IPC: G06F12/0831 ,  G06F12/0808

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

公开(公告)号：US11055250B2

公开(公告)日：2021-07-06

申请号：US16593127

申请日：2019-10-04

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Damien Guillaume Pierre Payet ,  Jamshed Jalal ,  Alex James Waugh

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

公开(公告)号：US10761987B2

公开(公告)日：2020-09-01

申请号：US16202171

申请日：2018-11-28

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Michael Filippo ,  Klas Magnus Bruce ,  Paul Gilbert Meyer

IPC: G06F12/0815 ,  G06F13/16

Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

公开(公告)号：US10713187B2

公开(公告)日：2020-07-14

申请号：US16521621

申请日：2019-07-25

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US20150149809A1

公开(公告)日：2015-05-28

申请号：US14092417

申请日：2013-11-27

Applicant: ARM LIMITED

Inventor： Brett Stanley FEERO ,  Klas Magnus Bruce

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F13/4059 ,  G06F2213/0038

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data. The transmission control circuitry includes tracking circuitry which stores one or more tracking values for tracking respective state variables of the first-in-first-out buffer and controlling whether or not the transmission control circuitry permits the sending of data from the source to the destination in dependence upon the generated control circuitry.

Abstract translation: 异步桥电路提供源时钟域中的源电路4与目的地时钟域中的目的地电路12之间的数据通信。 异步桥电路包括先进先出缓冲器20，传输路径电路14，其具有耦合到源电路的输入端和耦合到先进先出缓冲器的输出端。 传输路径电路具有对应于多个源时钟周期的传输延迟。 写指针电路22位于传输路径电路的输出端18处的源时钟域内，以便产生用于先进先出缓冲器的写指针。 位于传输路径电路的输入端16处的源时钟域内的传输控制电路26被配置为产生控制是否允许源电路发送数据的传输控制信号。 传输控制电路包括跟踪电路，其存储用于跟踪先进先出缓冲器的各个状态变量的一个或多个跟踪值，并且控制传输控制电路是否允许从源到目的地的数据发送 依赖于所产生的控制电路。

公开(公告)号：US11841800B2

公开(公告)日：2023-12-12

申请号：US17225614

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Jamshed Jalal ,  Steven Douglas Krueger ,  Klas Magnus Bruce

IPC: G06F12/08 ,  G06F12/0842 ,  G06F12/10 ,  G06F13/40

CPC classification number: G06F12/0842 ,  G06F12/10 ,  G06F13/4027 ,  G06F2212/1024 ,  G06F2212/608

Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request. The stash request handling circuitry is then responsive to the corresponding physical address determined by the address translation circuitry to cause the block of data to be stored at a location within the storage structure associated with the physical address.

公开(公告)号：US11200177B2

公开(公告)日：2021-12-14

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James Waugh ,  Dimitrios Kaseridis ,  Klas Magnus Bruce ,  Michael Filippo ,  Joseph Michael Pusdesris ,  Jamshed Jalal

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

公开(公告)号：US10579526B2

公开(公告)日：2020-03-03

申请号：US15427410

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/16

Abstract: A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.