公开(公告)号：US09281027B1

公开(公告)日：2016-03-08

申请号：US14511581

申请日：2014-10-10

Applicant: ARM LIMITED

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Mudit Bhargava

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/419 ,  G11C29/04

Abstract: A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path. Said latching circuitry outputs said latching value as said output in dependence on said enable signal, such that said enable signal controls both said latching circuitry and said sense circuitry.

Abstract translation: 存储器件包括用于接收锁存值并用于提供所述锁存值作为输出的锁存电路。 路径接收所述锁存值并将所述锁存值传递到所述锁存电路。 当所述存储器件处于读取操作模式时，第一存储电路提供第一存储值。 位线连接到所述第一存储电路。 第一控制电路选择性地将所述位线连接到所述路径。 感测电路，当使能信号有效时，由于将所述位线连接到所述第一存储电路和所述路径而检测所述路径上的电压变化，并根据所述电压变化在所述路径上输出锁存值。 第二存储电路在测试操作模式中提供第二存储值，第二控制电路接收所述第二存储值，并且有选择地将所述第二存储值输出作为所述路径上的锁存值。 所述锁存电路根据所述使能信号输出所述锁存值作为所述输出，使得所述使能信号控制所述锁存电路和所述检测电路。

公开(公告)号：US12159659B2

公开(公告)日：2024-12-03

申请号：US17107725

申请日：2020-11-30

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Pranay Prabhat ,  Fernando Garcia Redondo

IPC: G11C11/16

Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.

公开(公告)号：US20230289576A1

公开(公告)日：2023-09-14

申请号：US17689755

申请日：2022-03-08

Applicant: Arm Limited

Inventor： Fernando García Redondo ,  Mudit Bhargava ,  Paul Nicholas Whatmough ,  Shidhartha Das

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/082

Abstract: Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.

公开(公告)号：US11521680B2

公开(公告)日：2022-12-06

申请号：US17139059

申请日：2020-12-31

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Mudit Bhargava ,  Pranay Prabhat ,  Supreet Jeloka

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

公开(公告)号：US11520658B2

公开(公告)日：2022-12-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton Irby ,  Wendy Arnott Elsasser ,  Mudit Bhargava ,  Yew Keong Chong ,  George McNeil Lattimore ,  James Dennis Dodrill

IPC: G06F11/10 ,  G11C5/14 ,  G11C7/10 ,  G11C29/12 ,  G06N20/00

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US20220246206A1

公开(公告)日：2022-08-04

申请号：US17162532

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C11/419 ,  G11C11/418

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

公开(公告)号：US20210097173A1

公开(公告)日：2021-04-01

申请号：US16584865

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Joshua Randall ,  Joel Thornton Irby ,  Carl Wayne Vineyard ,  Mudit Bhargava

IPC: G06F21/55 ,  H03K19/003 ,  G11C13/00

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

公开(公告)号：US10896730B1

公开(公告)日：2021-01-19

申请号：US16457808

申请日：2019-06-28

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

IPC: G11C14/00 ,  G11C11/16 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

Abstract: In a particular implementation, a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising: for each of the D-MRAM bit-cells: writing a first data value in a storage capacitor; and in a first cycle, providing a first voltage to a source line coupled to an ME-MTJ, wherein in response to the storage capacitor storing the first data value, the ME-MTJ is configured to store the first data value if the first voltage generates a voltage difference between first and second terminals of the ME-MTJ.

公开(公告)号：US10854291B2

公开(公告)日：2020-12-01

申请号：US16167822

申请日：2018-10-23

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava ,  George McNeil Lattimore

IPC: G11C14/00 ,  G11C5/06 ,  G11C5/14 ,  G11C11/419

Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

公开(公告)号：US20200302996A1

公开(公告)日：2020-09-24

申请号：US16359758

申请日：2019-03-20

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

IPC: G11C11/419 ,  G11C16/12 ,  G11C16/08

Abstract: In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.