公开(公告)号：US11409617B2

公开(公告)日：2022-08-09

申请号：US16882402

申请日：2020-05-22

Applicant: Arm Limited

Inventor： Emily Kathryn Ruppel ,  Supreet Jeloka ,  Parameshwarappa Anand Kumar Savanth ,  Wei Wang

IPC: G06F11/00 ,  G06F11/14 ,  H02J50/00 ,  G06F1/26

Abstract: Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

公开(公告)号：US10726908B2

公开(公告)日：2020-07-28

申请号：US16107707

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Pranay Prabhat ,  James Edward Myers

IPC: G11C11/418 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4091 ,  G11C8/14 ,  G11C8/16 ,  G11C16/28

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.

公开(公告)号：US12080378B2

公开(公告)日：2024-09-03

申请号：US17709076

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Fernando García Redondo ,  Pranay Prabhat ,  Mudit Bhargava ,  Supreet Jeloka

IPC: G11C7/12 ,  G11C5/12 ,  G11C7/16 ,  G11C7/18 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/12 ,  G11C7/16 ,  G11C7/18 ,  G11C8/08

Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

公开(公告)号：US20230317126A1

公开(公告)日：2023-10-05

申请号：US17709076

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Fernando García Redondo ,  Pranay Prabhat ,  Mudit Bhargava ,  Supreet Jeloka

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/16 ,  G11C8/08 ,  G11C5/12

CPC classification number: G11C7/12 ,  G11C7/18 ,  G11C7/16 ,  G11C8/08 ,  G11C5/12

Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

公开(公告)号：US20220399895A1

公开(公告)日：2022-12-15

申请号：US17344390

申请日：2021-06-10

Applicant: Arm Limited

Inventor： Shidhartha Das ,  Yunpeng Cai ,  Supreet Jeloka

IPC: H03L7/099 ,  H03L7/187 ,  H03L7/081 ,  H03L7/199 ,  H03L7/091

Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

公开(公告)号：US20220382690A1

公开(公告)日：2022-12-01

申请号：US17334960

申请日：2021-05-31

Applicant: Arm Limited

Inventor： Paul Nicholas Whatmough ,  Zhi-Gang Liu ,  Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Matthew Mattina

IPC: G06F13/16 ,  G06F13/40

Abstract: Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.

公开(公告)号：US20220164127A1

公开(公告)日：2022-05-26

申请号：US17103632

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

IPC: G06F3/06 ,  G06N3/063

Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.

公开(公告)号：US11081469B2

公开(公告)日：2021-08-03

申请号：US16580349

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar Sinha ,  Joel Thornton Irby ,  Supreet Jeloka

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

公开(公告)号：US12223010B2

公开(公告)日：2025-02-11

申请号：US17339895

申请日：2021-06-04

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Rahul Mathur

IPC: G06F17/16 ,  G06F9/30

Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

公开(公告)号：US12086453B2

公开(公告)日：2024-09-10

申请号：US17103632

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

IPC: G11C16/04 ,  G06F3/06 ,  G06N3/063 ,  G11C11/54

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/063 ,  G11C11/54

Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.