Ultra wide band signal generator
    11.
    发明申请
    Ultra wide band signal generator 有权
    超宽带信号发生器

    公开(公告)号:US20060197617A1

    公开(公告)日:2006-09-07

    申请号:US11345716

    申请日:2006-02-02

    IPC分类号: H03B1/00

    摘要: Disclosed is an ultra wide band signal generator. The ultra wide band signal generator generates a signal of a required frequency using a harmonic signal having a frequency range of a ultra wide band (UWB). The ultra wide band signal generator includes an active inductor for generating harmonic signals having power strengths substantially equal to each other within a non-linear operation range, the tunable active inductor capable of tuning a value thereof, an oscillator for amplifying and outputting the harmonic signals generated from the active inductor by frequency-transiting the harmonic signals into high frequency bands, and a filter for selectively outputting one of the harmonic signals output from the oscillator.

    摘要翻译: 公开了一种超宽带信号发生器。 超宽带信号发生器使用具有超宽带(UWB)的频率范围的谐波信号产生所需频率的信号。 超宽带信号发生器包括有源电感器,用于产生具有在非线性运行范围内彼此基本相等的功率强度的谐波信号,该可调谐有源电感器能调谐其值,用于放大和输出谐波信号的振荡器 通过将谐波信号频率转换成高频带从有源电感器产生的滤波器以及用于选择性地输出从振荡器输出的谐波信号之一的滤波器。

    Input matching circuit for multiband low noise amplifier
    12.
    发明授权
    Input matching circuit for multiband low noise amplifier 失效
    多频低噪声放大器输入匹配电路

    公开(公告)号:US07253688B2

    公开(公告)日:2007-08-07

    申请号:US11088591

    申请日:2005-03-24

    IPC分类号: H03F3/191 H03F1/22

    摘要: Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.

    摘要翻译: 提供了一种包括第一晶体管,输入匹配电路和第一电容器的多频带低噪声放大器。 第一晶体管包括电连接到第一电源,接地发射极和与第一电感器的另一端连接的基极的集电极,第一电感器的一端作为低噪声放大器的输入端。 输入匹配电路连接在第一晶体管的集电极和基极之间。 第一个电容连接到第一个transistior的收集器。 输入匹配电路包括变容二极管。 输入匹配电路包括连接到变容二极管的第二电容器。 输入匹配电路包括连接到变容二极管的第一电阻器。 在多频带低噪声放大器中,具有可变电容的变容二极管安装在输入端,从而通过少量的偏置电压控制容易地执行频带切换并且最小化可能由控制信号引起的噪声。

    Local oscillation circuit for direct conversion receiver
    13.
    发明申请
    Local oscillation circuit for direct conversion receiver 审中-公开
    用于直接转换接收器的本地振荡电路

    公开(公告)号:US20060194556A1

    公开(公告)日:2006-08-31

    申请号:US11345738

    申请日:2006-02-02

    IPC分类号: H04B1/06 H04B1/26

    CPC分类号: H04B1/30

    摘要: Disclosed is a local oscillation circuit for a direct conversion receiver, which includes a local oscillator for outputting a local oscillation signal of a predetermined frequency; and a fractional signal generator for converting the local oscillation signal into a fractional harmonic signal, which has a frequency equal to a frequency of a received signal, and outputting the converted signal to a down converter. The fractional signal generator includes a divider for dividing a frequency of an output signal of the fractional signal generator by a predetermined integer; and a mixer for mixing the local oscillation signal and an output signal of the divider.

    摘要翻译: 公开了一种用于直接转换接收机的本地振荡电路,其包括用于输出预定频率的本地振荡信号的本地振荡器; 以及分数信号发生器,用于将本地振荡信号转换成具有等于接收信号的频率的频率的分数谐波信号,并将转换的信号输出到下变频器。 分数信号发生器包括用于将分数信号发生器的输出信号的频率除以预定整数的分频器; 以及用于混合本地振荡信号和分频器的输出信号的混频器。

    HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS
    14.
    发明申请
    HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS 有权
    高速脉冲形状滤波器系统和方法

    公开(公告)号:US20090140784A1

    公开(公告)日:2009-06-04

    申请号:US12327279

    申请日:2008-12-03

    IPC分类号: H03L7/00 H03K5/01

    CPC分类号: H03H15/00 H03H2015/002

    摘要: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.

    摘要翻译: 第一系统和方法涉及使用分支系统的模拟电流模式方法。 在模拟电流模式实现中,可以根据滤波器系数对多个分支系统进行缩放,并使用已知的数据点进行切换。 正系数可以向求和节点添加电流,而负系数可以从求和节点去除电流。 开关可以通过快速充电/放电路径实现,以便以非常高的数据速率运行。 第二系统和方法涉及基于数字查找表的高速实现。 在数字实现中,可以将输出预先计算为驱动n位DAC的n位输出字。 n位字的每个位可以被描述为已知数据点的独立函数。 每个这样的功能可以被实现为高速组合逻辑块。 这两种系统和方法使得能够实现用于千兆位/秒数据传输的脉冲整形滤波器。

    High-speed pulse shaping filter systems and methods
    15.
    发明授权
    High-speed pulse shaping filter systems and methods 有权
    高速脉冲整形滤波系统及方法

    公开(公告)号:US08473535B2

    公开(公告)日:2013-06-25

    申请号:US12327279

    申请日:2008-12-03

    IPC分类号: G06F17/10

    CPC分类号: H03H15/00 H03H2015/002

    摘要: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.

    摘要翻译: 第一系统和方法涉及使用分支系统的模拟电流模式方法。 在模拟电流模式实现中,可以根据滤波器系数对多个分支系统进行缩放,并使用已知的数据点进行切换。 正系数可以向求和节点添加电流,而负系数可以去除求和节点的电流。 开关可以通过快速充电/放电路径实现,以便以非常高的数据速率运行。 第二系统和方法涉及基于数字查找表的高速实现。 在数字实现中,可以将输出预先计算为驱动n位DAC的n位输出字。 n位字的每个位可以被描述为已知数据点的独立函数。 每个这样的功能可以被实现为高速组合逻辑块。 这两种系统和方法使得能够实现用于千兆位/秒数据传输的脉冲整形滤波器。

    Analog signal processor in a multi-gigabit receiver system
    16.
    发明授权
    Analog signal processor in a multi-gigabit receiver system 有权
    模拟信号处理器在一个多吉比特接收机系统中

    公开(公告)号:US08081948B2

    公开(公告)日:2011-12-20

    申请号:US12447163

    申请日:2007-10-25

    IPC分类号: H04B1/16

    CPC分类号: G06G7/12

    摘要: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.

    摘要翻译: 可以实现模拟多吉比特接收机和/或收发机用于使用CMOS(互补金属氧化物半导体)工艺调制的多吉比特正交相移键控(QPSK)的接收和解调。 此外,可以实现模拟多吉比特接收机和/或收发器用于接收和解调多吉比特二进制相移键控(BPSK),最小移位键控(MSK)和/或幅度键控(ASK)信号调制 在CMOS工艺中。

    ANALOG SIGNAL PROCESSOR IN A MULTI-GIGABIT RECEIVER SYSTEM
    17.
    发明申请
    ANALOG SIGNAL PROCESSOR IN A MULTI-GIGABIT RECEIVER SYSTEM 有权
    多功能接收机系统中的模拟信号处理器

    公开(公告)号:US20100093299A1

    公开(公告)日:2010-04-15

    申请号:US12447163

    申请日:2007-10-25

    IPC分类号: H04B17/00 H04B1/16

    CPC分类号: G06G7/12

    摘要: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.

    摘要翻译: 可以实现模拟多吉比特接收机和/或收发机用于使用CMOS(互补金属氧化物半导体)工艺调制的多吉比特正交相移键控(QPSK)的接收和解调。 此外,可以实现模拟多吉比特接收机和/或收发器用于接收和解调多吉比特二进制相移键控(BPSK),最小移位键控(MSK)和/或幅度键控(ASK)信号调制 在CMOS工艺中。

    Systems, methods and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using switched resonators
    18.
    发明授权
    Systems, methods and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using switched resonators 有权
    使用开关谐振器的互补金属氧化物半导体(CMOS)天线开关的系统,方法和装置

    公开(公告)号:US08165535B2

    公开(公告)日:2012-04-24

    申请号:US11754103

    申请日:2007-05-25

    IPC分类号: H04B1/44

    CPC分类号: H04B1/48

    摘要: Systems and methods may be provided for a CMOS RF antenna switch. The systems and methods for the CMOS RF antenna switch may include an antenna that is operative to transmit and receive signals over at least one radio frequency (RF) band, and a transmit switch coupled to the antenna, where the transmit switch is enabled to transmit a respective first signal to the antenna and disabled to prevent transmission of the first signal to the antenna. the systems and methods for the CMOS RF antenna switch may further include a receiver switch coupled to the antenna, where the receiver switch forms a filter when enabled and a resonant circuit when disabled, where the filter provides for reception of a second signal received by the antenna, and where the resonant circuit blocks reception of at least the first signal.

    摘要翻译: 可以为CMOS RF天线开关提供系统和方法。 CMOS RF天线开关的系统和方法可以包括可操作以通过至少一个射频(RF)频带发送和接收信号的天线,以及耦合到天线的发射开关,其中发射开关能够传输 对天线的相应的第一信号并且禁止阻止第一信号传输到天线。 用于CMOS RF天线开关的系统和方法还可以包括耦合到天线的接收器开关,其中接收器开关在使能时形成滤波器,当禁用时形成谐振电路,其中滤波器提供接收由第 天线,并且其中谐振电路阻止至少第一信号的接收。

    Systems and methods for determining sensing thresholds of a multi-resolution spectrum sensing (MRSS) technique for cognitive radio (CR) systems
    19.
    发明授权
    Systems and methods for determining sensing thresholds of a multi-resolution spectrum sensing (MRSS) technique for cognitive radio (CR) systems 有权
    用于确定用于认知无线电(CR)系统的多分辨率频谱感测(MRSS)技术的感测阈值的系统和方法

    公开(公告)号:US07768252B2

    公开(公告)日:2010-08-03

    申请号:US12034570

    申请日:2008-02-20

    IPC分类号: G01R23/00

    CPC分类号: H04W8/005 H04W16/14 H04W16/22

    摘要: Systems and methods may be provided for threshold determinations for spectrum sensing. The systems and methods may include receiving a false alarm rate, where the false alarm rate is associated with false occupancy identifications of a spectrum segment, determining a noise floor as a function of a noise figure and characteristics of a multi-resolution spectrum sensing (MRSS) window, and calculating a sensing threshold based at least in part upon the false alarm rate and the noise floor. The systems and methods may also include determining whether a portion of an RF spectrum is occupied based at least in part on the calculated sensing threshold.

    摘要翻译: 可以提供用于频谱感测的阈值确定的系统和方法。 系统和方法可以包括接收误报率,其中误报率与频谱段的假占用标识相关联,确定作为噪声系数和多分辨率频谱感测特性(MRSS)的函数的本底噪声 )窗口,并且至少部分地基于所述误报率和所述本底噪声来计算感测阈值。 系统和方法还可以包括至少部分地基于所计算的感测阈值来确定RF频谱的一部分是否被占用。