公开(公告)号：US06229177B1

公开(公告)日：2001-05-08

申请号：US09050747

申请日：1998-03-30

Applicant: Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

Inventor： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

IPC: H01L2976

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045

Abstract: An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

Abstract translation: 具有横向不均匀沟道掺杂分布的超大规模集成电路半导体器件通过以垂直于0°至60°的注入角度使用IV族元件注入来制造，以在掺杂硅衬底中产生间隙 半导体器件的栅极。 在创建间隙之后，使用也与从垂直方向成0°至60°的植入角度植入的III族或V族元件进行沟道掺杂注入。 然后使用快速热退火来通过瞬时增强的扩散将掺杂剂横向驱动到半导体器件的沟道中。

公开(公告)号：US6087255A

公开(公告)日：2000-07-11

申请号：US127887

申请日：1998-08-03

Applicant: Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

Inventor： Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

IPC: H01L21/027 ,  H01L21/768 ,  H01L31/0236

CPC classification number: H01L21/76886 ,  H01L21/0276 ,  H01L21/76888 ,  Y10S438/952

Abstract: The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface of the conductive layer to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface of an aluminum or an aluminum-alloy conductive layer to render the upper portion substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

Abstract translation: 避免了在光刻处理期间在导电层上施加不同的抗反射涂层，因为通过改变导电层的上表面的一部分以表现出抗反射性能。 在本发明的一个实施例中，杂质离子被注入到铝或铝合金导电层的上表面的一部分中，以使上部基本上是非晶的，因此降低其反射率以进行抗反射功能 。

公开(公告)号：US5940735A

公开(公告)日：1999-08-17

申请号：US917149

申请日：1997-08-25

Applicant: Sunil D. Mehta ,  Che-Hoo Ng

Inventor： Sunil D. Mehta ,  Che-Hoo Ng

IPC: H01L21/28 ,  H01L21/3115 ,  H01L21/318 ,  H01L21/322 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00

CPC classification number: H01L21/76832 ,  H01L21/31155 ,  H01L21/3221 ,  H01L21/76834 ,  H01L29/66825

Abstract: A semiconductor device formed in a semiconductor substrate with a low hydrogen content barrier layer formed over the semiconductor device. The barrier layer is implanted with phosphorus ions. The semiconductor device may have a hydrogen getter layer formed under the barrier layer. The barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between 1000 and 2000 Angstroms and is a PSG, BPSG, PTEOS deposited oxide film, or BPTEOS deposited oxide film. Interconnects are made by a tungsten damascene process.

Abstract translation: 形成在半导体衬底上的半导体器件，其具有形成在半导体器件上的低氢含量阻挡层。 阻挡层注入磷离子。 半导体器件可以具有形成在阻挡层下面的吸氢剂层。 阻挡层是高温PECVD氮化物膜，高温PECVD氮氧化物膜或高温LPCVD氮化物膜。 吸氢剂层是厚度在1000和2000埃之间的P掺杂膜，是PSG，BPSG，PTEOS沉积氧化膜或BPTEOS沉积氧化物膜。 互连由钨镶嵌工艺制成。

公开(公告)号：US06624037B2

公开(公告)日：2003-09-23

申请号：US09918794

申请日：2001-08-01

Applicant: Matthew Stephen Buynoski ,  Che-Hoo Ng

Inventor： Matthew Stephen Buynoski ,  Che-Hoo Ng

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/324 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

Abstract: A SOI substrate is preamorphized by ion implanting Xe prior to forming source/drain extensions and source/drain regions, thereby virtually eliminating or significantly reducing floating body effects. Other aspects comprise ion implanting a Xe2+ into a bulk silicon or SOI substrate to effect preeamorphization prior to forming source/drain extensions and regions having shallow junctions with reduced vertical and lateral straggle.

Abstract translation: 在形成源极/漏极延伸部分和源极/漏极区域之前，通过离子注入Xe来改变SOI衬底，从而实际上消除或显着减少浮体效应。 其他方面包括将Xe2 +离子注入到体硅或SOI衬底中，以在形成源极/漏极延伸部分之前实现预变形，并且具有具有减少的垂直和横向倾斜的浅结的区域。

公开(公告)号：US06288405B1

公开(公告)日：2001-09-11

申请号：US09295937

申请日：1999-04-21

Applicant: Che-Hoo Ng

Inventor： Che-Hoo Ng

IPC: H01J37317

CPC classification number: H01L22/34 ,  H01J37/3171 ,  H01J2237/31703

Abstract: A method for determining a dosimetry of a semiconductor substrate is provided which is accurate, reliable, simple and inexpensive. The present invention is especially useful for determining dosimetry of ultra shallow junctions formed using low energy implantation commonly found in sub−0.25 &mgr;m technologies. In a preferred embodiment, a material layer of a thickness is formed over a semiconductor substrate, followed by an ion implantation of a dopant. The material layer is then analyzed using a chemical method such as vapor phase plasma deposition inductively coupled plasma mass spectroscopy with atomic absorption (VPD-ICPMS-AA) to determine the amount of dopant present in the material layer.

Abstract translation: 提供了一种确定半导体衬底的剂量测定方法，其准确，可靠，简单且便宜。 本发明特别可用于确定通过在0.25μm以下的技术中常见的低能量注入形成的超浅结的剂量测定。 在优选实施例中，在半导体衬底上形成厚度的材料层，然后进行掺杂剂的离子注入。 然后使用诸如气相等离子体沉积电感耦合等离子体质谱与原子吸收（VPD-ICPMS-AA）的化学方法分析材料层，以确定材料层中存在的掺杂剂的量。

公开(公告)号：US6146944A

公开(公告)日：2000-11-14

申请号：US39783

申请日：1998-03-16

Applicant: Yue-Song He ,  Che-Hoo Ng ,  Pau-Ling Chen

Inventor： Yue-Song He ,  Che-Hoo Ng ,  Pau-Ling Chen

IPC: H01L21/265 ,  H01L21/8247

CPC classification number: H01L27/11517 ,  H01L21/26586

Abstract: A P-type dopant is implanted into a substrate region 94 under a select drain gate transistor field oxide region 75 at a large tilt angle .alpha., to prevent field turn-on under the select drain gate transistor field oxide region 75 in a non-volatile memory device such as a NAND flash memory device. A substrate region 114 under a select source gate transistor field oxide region 77 can also be implanted with a P-type dopant to prevent field turn-on under the region 77 if select source gates 90 and 92 are to be supplied with a voltage in operation rather than grounded. The substrate regions 94 and 114 under both the select drain gate transistor field oxide region 75 and the select source gate transistor field oxide region 77 can be implanted with the P-type dopant using a fixed-angle ion beam 120, by rotating the wafer 124 between the step of implanting one of the substrate regions and the step of implanting the other region.

Abstract translation: P型掺杂剂以大的倾斜角α被注入到选择漏极栅极晶体管场氧化物区域75下方的衬底区域94中，以防止选择漏极栅极晶体管场氧化物区域75在非易失性 诸如NAND闪存器件的存储器件。 选择源栅极晶体管场氧化物区域77下方的衬底区域114也可以注入P型掺杂剂，以防止在选择源极栅极90和92被施加电压时在区域77下的场导通 而不是接地。 在选择漏极栅极晶体管场氧化物区域75和选择源极栅极晶体管场氧化物区域77两者之下的衬底区域94和114可以使用固定角度离子束120注入P型掺杂剂，通过旋转晶片124 在植入一个衬底区域的步骤和植入另一个区域的步骤之间。

公开(公告)号：US6136674A

公开(公告)日：2000-10-24

申请号：US245727

申请日：1999-02-08

Applicant: Judy X. An ,  Che-Hoo Ng

Inventor： Judy X. An ,  Che-Hoo Ng

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device is formed having a gate electrode and a gate oxide comprising a central portion and edge portions having a thickness greater than that of the edge portions. Nitrogen is ion implanted into the surface of the semiconductor substrate to retard the growth of the central portion of the gate oxide, thereby enabling formation of gate oxide having a thin central portion and thicker edge portions.

Abstract translation: 形成具有栅电极和栅氧化物的半导体器件，栅极氧化物包括中心部分和具有大于边缘部分的厚度的边缘部分。 将氮离子注入到半导体衬底的表面中以阻止栅极氧化物的中心部分的生长，从而能够形成具有薄的中心部分和较厚的边缘部分的栅极氧化物。

公开(公告)号：US5841179A

公开(公告)日：1998-11-24

申请号：US704162

申请日：1996-08-28

Applicant: Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

Inventor： Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

IPC: H01L21/027 ,  H01L21/768 ,  H01L31/0236

CPC classification number: H01L21/76886 ,  H01L21/0276 ,  H01L21/76888 ,  Y10S438/952

Abstract: The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface of the conductive layer to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface of an aluminum or an aluminum-alloy conductive layer to render the upper portion substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

公开(公告)号：US06452198B1

公开(公告)日：2002-09-17

申请号：US09893847

申请日：2001-06-28

Applicant: Balaraman Mani ,  Bill Chen ,  Che-Hoo Ng

Inventor： Balaraman Mani ,  Bill Chen ,  Che-Hoo Ng

IPC: H01J3720

CPC classification number: H01J37/3171

Abstract: Contamination of semiconductor wafers are minimized during implantation processes within an implantation system. An implantation chamber of the implantation system and components within the implantation chamber are coated with additional material to minimize contaminants within the implantation chamber. For example, surfaces of the implantation chamber and/or the components of the implantation chamber are coated by performing an implantation process with a coating dopant before a semiconductor wafer is placed within the implantation chamber. In this manner, contaminants on the surfaces of the implantation chamber and/or the components within the implantation chamber are substantially coated and encapsulated with the coating dopant to prevent contact of the contaminant with the semiconductor wafer placed within the implantation chamber. Alternatively, shields are placed on surfaces of the implantation chamber and/or on surfaces of the components of the implantation chamber during an implantation process for a first semiconductor wafer having a contaminant source. Such shields are amenable for absorbing the contaminant and are removed after this implantation process and before a second semiconductor wafer is placed within the implantation chamber to minimize contamination of the second semiconductor wafer.

Abstract translation: 在植入系统内的植入过程期间，半导体晶片的污染被最小化。 植入系统的植入室和植入室内的组件涂覆有额外的材料以最小化植入室内的污染物。 例如，在将半导体晶片放置在植入室内之前，通过执行具有涂层掺杂剂的注入工艺来涂覆注入室的表面和/或注入室的部件。 以这种方式，植入室表面上的污染物和/或植入室内的组分被涂覆掺杂剂基本上涂覆和封装，以防止污染物与放置在植入室内的半导体晶片的接触。 或者，在具有污染源的第一半导体晶片的注入过程期间，将屏蔽物放置在注入室的表面和/或植入室的部件的表面上。 这种屏蔽件适于吸收污染物并且在该注入工艺之后并且在将第二半导体晶片放置在注入室内之前被去除以最小化第二半导体晶片的污染。

公开(公告)号：US06235636B1

公开(公告)日：2001-05-22

申请号：US09295271

申请日：1999-04-20

Applicant: Che-Hoo Ng ,  Matthew S. Buynoski

Inventor： Che-Hoo Ng ,  Matthew S. Buynoski

IPC: H01L21302

CPC classification number: H01L21/31053 ,  H01L21/0273

Abstract: Chemical mechanical polishing for removing a hardened surface layer of photoresist in the manufacture of semiconductor devices. The use of chemical mechanical polishing allows for the removal of a hardened surface layer of photoresist that has been hardened through ion beam implantation or plasma etching. The chemical mechanical polishing process places a semiconductor wafer with a photoresist layer on a polishing pad. The photoresist layer is placed close to the polishing pad, so that the hardened surface layer of the photoresist layer is removed. A slurry is added to the polishing pad to aid in the removal of the hardened surface layer of the photoresist layer. Conventional chemical stripping is then used to remove the remaining photoresist layer.

Abstract translation: 在半导体器件的制造中去除光刻胶的硬化表面层的化学机械抛光。 使用化学机械抛光允许去除通过离子束注入或等离子体蚀刻而硬化的光致抗蚀剂的硬化表面层。 化学机械抛光工艺将具有光致抗蚀剂层的半导体晶片放置在抛光垫上。 将光致抗蚀剂层置于靠近抛光垫的位置，从而去除光致抗蚀剂层的硬化表面层。 将浆料添加到抛光垫中以帮助去除光致抗蚀剂层的硬化表面层。 然后使用常规的化学剥离来除去剩余的光致抗蚀剂层。