公开(公告)号：US06200869B1

公开(公告)日：2001-03-13

申请号：US09187890

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US6084271A

公开(公告)日：2000-07-04

申请号：US187892

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

公开(公告)号：US20060177998A1

公开(公告)日：2006-08-10

申请号：US11379435

申请日：2006-04-20

Applicant: Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

IPC: H01L21/3205

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Abstract translation: 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

公开(公告)号：US06670260B1

公开(公告)日：2003-12-30

申请号：US09577332

申请日：2000-05-24

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06342438B2

公开(公告)日：2002-01-29

申请号：US09187379

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21265

CPC classification number: H01L21/823842 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823871

Abstract: A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.

Abstract translation: 双掺杂CMOS栅极结构利用氮注入来抑制掺杂剂相互扩散。 在标准沟槽隔离结构之上提供氮注入。 或者，可以使用氧注入。 使用植入物可以提高超大规模集成（ULSI）电路的封装密度。 当掺杂多晶硅栅极结构时，可以完成N沟道和P沟道有源区的掺杂。

公开(公告)号：US06262456B1

公开(公告)日：2001-07-17

申请号：US09187842

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L31113

CPC classification number: H01L29/6659 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/105 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括具有多晶硅材料的栅极结构。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。

公开(公告)号：US08222680B2

公开(公告)日：2012-07-17

申请号：US10274961

申请日：2002-10-22

Applicant: Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract translation: 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

公开(公告)号：US07416925B2

公开(公告)日：2008-08-26

申请号：US11677404

申请日：2007-02-21

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US07250645B1

公开(公告)日：2007-07-31

申请号：US10761374

申请日：2004-01-22

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L29/76 ,  H01L27/08

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7842

Abstract: A fin field effect transistor (FinFET) includes a reversed T-shaped fin. The FinFET further includes source and drain regions formed adjacent the reversed T-shaped fin. The FinFET further includes a dielectric layer formed adjacent surfaces of the fin and a gate formed adjacent the dielectric layer.

Abstract translation: 翅片场效应晶体管（FinFET）包括反转的T形翅片。 FinFET还包括邻近反转的T形翅片形成的源极和漏极区域。 FinFET还包括邻近散热片表面形成的电介质层和邻近电介质层形成的栅极。

公开(公告)号：US06852576B2

公开(公告)日：2005-02-08

申请号：US10825175

申请日：2004-04-16

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method forms fin structures for a semiconductor device. The method includes forming a first fin structure including a dielectric material and including a first side surface and a second side surface; forming a second fin structure adjacent the first side surface of the first fin structure; and forming a third fin structure adjacent the second side surface of the first fin structure. The second fin structure and the third fin structure are formed of a different material than the first fin structure.

Abstract translation: 一种形成半导体器件的鳍结构的方法。 该方法包括形成包括电介质材料并包括第一侧表面和第二侧表面的第一鳍结构; 在所述第一翅片结构的第一侧表面附近形成第二鳍结构; 以及在所述第一翅片结构的所述第二侧表面附近形成第三鳍​​结构。 第二翅片结构和第三翅片结构由与第一翅片结构不同的材料形成。