公开(公告)号：US5486772A

公开(公告)日：1996-01-23

申请号：US268755

申请日：1994-06-30

申请人： Fwu-Iuan Hshieh ,  Calvin K. Choi ,  William H. Cook ,  Lih-Ying Ching ,  Mike F. Chang

发明人： Fwu-Iuan Hshieh ,  Calvin K. Choi ,  William H. Cook ,  Lih-Ying Ching ,  Mike F. Chang

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L29/78

CPC分类号： G01R31/2621

摘要： The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the present invention, a negative voltage is applied to the gate of the trench transistor with its drain grounded and its source floating. A leakage current flowing between the gate and drain is measured as a function of the voltage applied to the gate. A transistor whose gate-drain leakage current exceeds a predetermined value at a specified gate voltage is deemed to be defective. In another embodiment of the present invention, the gate-drain leakage current is measured as described above and monitored over time. Charge accumulated near the gate-drain interface due to defects in the interface results in the gate-drain leakage current taking a longer period of time to fall off to its steady state value. Accordingly, if the leakage current of a particular trench transistor does not fall off to a predetermined value within a predetermined amount of time, the transistor is deemed to be defective. The minimum/maximum allowable gate-drain leakage current published in a data sheet for the trench transistor will provide consumers with additional assurance of the transistor's long term reliability.

摘要翻译： 本发明检测沟槽晶体管的栅极/沟槽表面界面附近的缺陷。 导致长期可靠性问题的接口附近的缺陷通常也会导致接口附近收费。 根据本发明的一个实施例，负电压被施加到沟槽晶体管的栅极，其漏极接地并且其源极漂移。 根据施加到栅极的电压来测量在栅极和漏极之间流动的漏电流。 栅极漏极泄漏电流在指定的栅极电压下超过预定值的晶体管被​​认为是有缺陷的。 在本发明的另一个实施例中，如上所述测量栅 - 漏泄漏电流并随时间监测。 由于界面缺陷，在栅极 - 漏极接口附近积聚的电荷导致栅极 - 漏极泄漏电流需要更长的时间来降低到其稳定状态值。 因此，如果特定沟槽晶体管的泄漏电流在预定时间内没有下降到预定值，则认为晶体管有缺陷。 在沟槽晶体管的数据手册中公布的最小/最大允许栅 - 漏泄漏电流将为消费者提供晶体管长期可靠性的额外保证。

公开(公告)号：US5468982A

公开(公告)日：1995-11-21

申请号：US253527

申请日：1994-06-03

申请人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

CPC分类号： H01L29/407 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/1095 ,  H01L29/4236

摘要： A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.

摘要翻译： 沟槽的DMOS晶体管具有改进的器件性能和生产产量。 在制造期间，在源区域注入步骤期间，单元沟槽角部，即两个沟槽相交的区域被覆盖在集成电路基板的主表面上，并具有阻挡光致抗蚀剂层，以便防止（阻挡）在这些区域中形成沟道 角落地区。 因此消除了穿通，并提高了可靠性，同时源极/漏极导通电阻仅略微增加。 沟槽拐角的阻塞在每个沟槽角处产生切口结构，由此源极区域不延伸到沟槽角部，而是相反地，下面相对掺杂的体区域延伸到沟槽角部。

公开(公告)号：US5341011A

公开(公告)日：1994-08-23

申请号：US31798

申请日：1993-03-15

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Hamza Yilmaz

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Hamza Yilmaz

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1095 ,  H01L29/7813 ,  H01L29/0847 ,  Y10S148/103 ,  Y10S438/965

摘要： A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

摘要翻译： 具有沟槽栅极的DMOS晶体管形成在衬底中，使得晶体管的P体区域可以形成得更重或更深，同时保持“短”通道。 这是通过在形成沟槽之前在P体区域内形成N +型源区的一部分，然后在形成在P体区域的一部分上形成的N +源区的相对较浅的延伸部进行第二注入和扩散来实现的 。 P体区域的增加的深度或掺杂浓度有利地降低P体区域的电阻，而短通道降低晶体管的导通电阻以提高性能。

公开(公告)号：US5821583A

公开(公告)日：1998-10-13

申请号：US610563

申请日：1996-03-06

申请人： Fwu-Iuan Hshieh ,  Lih-Ying Ching ,  Hoang Tran ,  Mike F. Chang

发明人： Fwu-Iuan Hshieh ,  Lih-Ying Ching ,  Hoang Tran ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

摘要： A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub is formed surrounding the P+ body region in order to enhance avalanche breakdown. Thus the epitaxial layer resistivity can be decreased to reduce device on-resistance, while the desired breakdown voltage is also achieved. The on-resistance is further reduced by adding a pre-initial oxidation implant, i.e. phosphorous for an N channel device or boron for a P channel device. This forms a more heavily doped JFET or pinch region at the bottom of the trench and in the upper portion of the drift region. This N JFET region (which is P doped for a P channel device) is more heavily doped than the underlying epitaxial layer and surrounds the trench bottom, thus reducing on-resistance by increasing local doping concentration where otherwise a parasitic JFET would be present.

摘要翻译： 沟槽DMOS晶体管显着降低导通电阻。 形成围绕P +体区域的轻掺杂P桶，以增强雪崩击穿。 因此，可以减小外延层电阻率以减少器件导通电阻，同时也实现期望的击穿电压。 通过添加预初始氧化注入，即用于N沟道器件的磷或用于P沟道器件的硼，进一步降低导通电阻。 这在沟槽的底部和漂移区域的上部形成更重掺杂的JFET或夹持区域。 该N JFET区域（P掺杂用于P沟道器件）比下面的外延层更重掺杂并且围绕沟槽底部，从而通过增加局部掺杂浓度来降低导通电阻，否则将存在寄生JFET。

公开(公告)号：US5689128A

公开(公告)日：1997-11-18

申请号：US533814

申请日：1995-08-21

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Kuo-In Chen ,  Richard K. Williams ,  Mohamed Darwish

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Kuo-In Chen ,  Richard K. Williams ,  Mohamed Darwish

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/0878 ,  H01L29/1095 ,  H01L29/7813

摘要： The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In a second version, a double epitaxial layer is used with a somewhat lower but still high energy deep P+body implant. In a third version, there is no deep P+body implant but only the double epitaxial layer is used. The cell density is improved to more than 12 million cells per square inch in each of the three versions.

摘要翻译： 通过克服深P +体区域的横向扩散的问题，增加沟槽DMOS晶体管的细胞密度。 这个问题在三个版本中解决了。 在第一版本中，使用高能量注入形成单个外延层形成深P +体区域。 在第二版本中，使用具有稍低但仍然高能量的深P +体植入物的双外延层。 在第三个版本中，没有深P +体植入，但仅使用双外延层。 在三个版本的每一个中，细胞密度提高到每平方英寸超过1200万个细胞。

公开(公告)号：US5639676A

公开(公告)日：1997-06-17

申请号：US603047

申请日：1996-02-16

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L29/407 ,  H01L29/404 ,  H01L29/7813

摘要： A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

摘要翻译： 使用七个掩模步骤制造出沟槽的DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +深体区域和晶体管的有源部分。 第二掩蔽步骤限定了端接区域中的绝缘氧化物。 因此，端接区域中的绝缘（氧化物）层比晶体管的有源区域厚，从而改善了处理过程中的工艺控制和减少了衬底污染。 此外，端接区域中较厚的场氧化物改善了电场分布，使得雪崩击穿发生在电池（有源）区而不是终端区，因此击穿电压行为更稳定和可预测。

公开(公告)号：US5981344A

公开(公告)日：1999-11-09

申请号：US658115

申请日：1996-06-04

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7802

摘要： To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low R.sub.DSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed. This underlying relatively highly conductive layer may, for example, be either substrate or a more highly doped epitaxial silicon layer.

摘要翻译： 为了减少穿透的敏感性，沟槽场效应晶体管的P体区域的沟道区域形成在轻掺杂的外延硅层中。 结果，沟道区域具有比背景外延硅更少的反掺杂并且具有更大的净P型掺杂剂浓度。 由于P体区域的较高的净掺杂剂浓度，P体区域的任一侧上的耗尽区域在给定电压下通过P体区域向内扩展得较少，从而使晶体管较不易受源极 - 漏极 打通 为了保持低的RDSon，当晶体管导通时，沿着晶体管的沟槽的侧壁形成的累积区的相对较高的导电率被用于形成从沟道区到下层相对高导电层的导电路径， 形成轻掺杂的外延层。 该底层相对高导电的层可以例如是衬底或更高掺杂的外延硅层。

公开(公告)号：US5750416A

公开(公告)日：1998-05-12

申请号：US479308

申请日：1995-06-07

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Jan Van der Linde ,  Yueh-Se Ho

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Jan Van der Linde ,  Yueh-Se Ho

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/7802 ,  Y10S148/126

摘要： A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after being grown. The drain electrode of the transistor is disposed on a bottom surface of the substrate upon which the transistor structure is formed. When the transistor is turned on, the channel region inverts thereby forming a conductive path from a source region, laterally through the inverted channel region, substantially vertically through a sinker region to the underlying substrate, through the substrate, and to the drain electrode.

摘要翻译： 功率场效应晶体管具有不由双扩散形成的横向延伸的沟道区。 通道区域可以在外延硅中形成，其在生长后不被掺杂。 晶体管的漏电极设置在形成晶体管结构的衬底的底表面上。 当晶体管导通时，沟道区域反转，从而从源极区域侧向穿过反向沟道区域，基本垂直地穿过沉降片区域到底层衬底，通过衬底和漏电极形成导电路径。

公开(公告)号：US5629543A

公开(公告)日：1997-05-13

申请号：US537157

申请日：1995-08-21

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Lih-Ying Ching ,  Sze H. Ng ,  William Cook

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Lih-Ying Ching ,  Sze H. Ng ,  William Cook

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/0878 ,  H01L29/7813 ,  H01L29/1095

摘要： A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

摘要翻译： 沟槽DMOS晶体管包括在漏极区域和上覆漂移区域之间形成的具有与漂移区域和漏极区域相同的掺杂类型的掩埋层区域。 掩埋层区域比漏极区域或漂移区域更高掺杂，并且由例如， 在上覆漂移区域的外延生长之前的植入。 通过为掩埋层区域提供优化的掺杂分布，确保在掩埋层区域/体区发生雪崩击穿。 因此，消除了源极导通电阻，因为现有技术的器件中存在的JFET区域被消除，同时器件的耐用性和可靠性得到提高。

公开(公告)号：US5578851A

公开(公告)日：1996-11-26

申请号：US625639

申请日：1996-03-29

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/407 ,  H01L29/404 ,  H01L29/7813

摘要： A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

摘要翻译： 使用七个掩模步骤制造出沟槽的DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +深体区域和晶体管的有源部分。 第二掩蔽步骤限定了端接区域中的绝缘氧化物。 因此，端接区域中的绝缘（氧化物）层比晶体管的有源区域厚，从而改善了处理过程中的工艺控制和减少了衬底污染。 此外，端接区域中较厚的场氧化物改善了电场分布，使得雪崩击穿发生在电池（有源）区而不是终端区，因此击穿电压行为更稳定和可预测。