公开(公告)号：US5767578A

公开(公告)日：1998-06-16

申请号：US634957

申请日：1996-04-19

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

IPC分类号： H01L23/29 ,  H01L23/367 ,  H01L23/373 ,  H01L23/34

CPC分类号： H01L23/3672 ,  H01L23/29 ,  H01L23/3732 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 钝化层是提供电绝缘和导热性的CVD金刚石膜。 去除衬底背面（通过研磨和/或CMP）以暴露沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片以两种版本刻成模具，而不需要进一步的包装。

公开(公告)号：US5757081A

公开(公告)日：1998-05-26

申请号：US603512

申请日：1996-02-20

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/48

CPC分类号： H01L23/3672 ,  H01L23/3738 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/977

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 通过研磨或CMP去除衬底背面以露出沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片刻成两个版本的模具，无需进一步包装。

公开(公告)号：US5753529A

公开(公告)日：1998-05-19

申请号：US444660

申请日：1995-05-19

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L21/302

CPC分类号： H01L23/3672 ,  H01L23/3738 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/977

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

公开(公告)号：US5468982A

公开(公告)日：1995-11-21

申请号：US253527

申请日：1994-06-03

申请人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

CPC分类号： H01L29/407 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/1095 ,  H01L29/4236

摘要： A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.

摘要翻译： 沟槽的DMOS晶体管具有改进的器件性能和生产产量。 在制造期间，在源区域注入步骤期间，单元沟槽角部，即两个沟槽相交的区域被覆盖在集成电路基板的主表面上，并具有阻挡光致抗蚀剂层，以便防止（阻挡）在这些区域中形成沟道 角落地区。 因此消除了穿通，并提高了可靠性，同时源极/漏极导通电阻仅略微增加。 沟槽拐角的阻塞在每个沟槽角处产生切口结构，由此源极区域不延伸到沟槽角部，而是相反地，下面相对掺杂的体区域延伸到沟槽角部。

公开(公告)号：US5639676A

公开(公告)日：1997-06-17

申请号：US603047

申请日：1996-02-16

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L29/407 ,  H01L29/404 ,  H01L29/7813

摘要： A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

摘要翻译： 使用七个掩模步骤制造出沟槽的DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +深体区域和晶体管的有源部分。 第二掩蔽步骤限定了端接区域中的绝缘氧化物。 因此，端接区域中的绝缘（氧化物）层比晶体管的有源区域厚，从而改善了处理过程中的工艺控制和减少了衬底污染。 此外，端接区域中较厚的场氧化物改善了电场分布，使得雪崩击穿发生在电池（有源）区而不是终端区，因此击穿电压行为更稳定和可预测。

公开(公告)号：US5578851A

公开(公告)日：1996-11-26

申请号：US625639

申请日：1996-03-29

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/407 ,  H01L29/404 ,  H01L29/7813

摘要： A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

摘要翻译： 使用七个掩模步骤制造出沟槽的DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +深体区域和晶体管的有源部分。 第二掩蔽步骤限定了端接区域中的绝缘氧化物。 因此，端接区域中的绝缘（氧化物）层比晶体管的有源区域厚，从而改善了处理过程中的工艺控制和减少了衬底污染。 此外，端接区域中较厚的场氧化物改善了电场分布，使得雪崩击穿发生在电池（有源）区而不是终端区，因此击穿电压行为更稳定和可预测。

公开(公告)号：US5316959A

公开(公告)日：1994-05-31

申请号：US928909

申请日：1992-08-12

申请人： Sze-Hon Kwan ,  Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

发明人： Sze-Hon Kwan ,  Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0619 ,  H01L29/7813

摘要： A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

摘要翻译： 使用六个掩模步骤制造沟槽DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +区域和晶体管的有源部分。 LOCOS工艺还通过降低氧化物台阶高度来消除现有技术结构中存在的多边形问题。 晶体管端接结构包括几个场环，每组相邻的场环由绝缘沟槽隔开，从而允许场环非常靠近在一起。 场环和沟槽以与有源晶体管的对应部分相同的步骤制造。

公开(公告)号：US5750416A

公开(公告)日：1998-05-12

申请号：US479308

申请日：1995-06-07

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Jan Van der Linde ,  Yueh-Se Ho

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Jan Van der Linde ,  Yueh-Se Ho

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/7802 ,  Y10S148/126

摘要： A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after being grown. The drain electrode of the transistor is disposed on a bottom surface of the substrate upon which the transistor structure is formed. When the transistor is turned on, the channel region inverts thereby forming a conductive path from a source region, laterally through the inverted channel region, substantially vertically through a sinker region to the underlying substrate, through the substrate, and to the drain electrode.

摘要翻译： 功率场效应晶体管具有不由双扩散形成的横向延伸的沟道区。 通道区域可以在外延硅中形成，其在生长后不被掺杂。 晶体管的漏电极设置在形成晶体管结构的衬底的底表面上。 当晶体管导通时，沟道区域反转，从而从源极区域侧向穿过反向沟道区域，基本垂直地穿过沉降片区域到底层衬底，通过衬底和漏电极形成导电路径。

公开(公告)号：US5904525A

公开(公告)日：1999-05-18

申请号：US646593

申请日：1996-05-08

申请人： Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Bosco Lan ,  Jowei Dun

发明人： Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Bosco Lan ,  Jowei Dun

IPC分类号： H01L21/26 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/0696 ,  Y10S148/126

摘要： A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.

摘要翻译： 一种用于形成具有在半导体衬底上形成的外延层上占据最小面积的深体区的沟槽DMOS晶体管的方法。 第一氧化物层形成在外延层上并且被图案化以限定将在其下形成深体区域的深体区域。 接下来，在形成覆盖深体区域的第二氧化物层和第一氧化物层的剩余部分之前，在每个深体区域中形成第一导电类型的扩散抑制区域。 然后去除第二氧化物层的部分以暴露扩散抑制区域的中心，从第二氧化物层留下第一氧化物层和氧化物侧壁间隔物以覆盖扩散抑制区域的周边。 然后执行第二导电类型的深体扩散，导致在侧壁间隔件之间的外延层中形成深体区。 由第一和第二氧化物层的剩余部分覆盖的扩散抑制区域的周边阻止深体扩散的横向扩散，而不显着抑制扩散深度。

公开(公告)号：US07595547B1

公开(公告)日：2009-09-29

申请号：US11151749

申请日：2005-06-13

申请人： Mike Chang ,  King Owyang ,  Yueh-Se Ho ,  Y. Mohammed Kasem ,  Lixiong Luo ,  Wei-Bing Chu

发明人： Mike Chang ,  King Owyang ,  Yueh-Se Ho ,  Y. Mohammed Kasem ,  Lixiong Luo ,  Wei-Bing Chu

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

摘要翻译： 半导体封装包括杯形并保持半导体管芯的引线框架。 引线框架与裸片的一侧上的端子电接触，并且引线框架的引线以这样的方式弯曲，使得引线的一部分与管芯的另一侧共面，其还包含一个或多个端子 。 在引线框架和模具周围形成塑料胶囊。