公开(公告)号：US5821583A

公开(公告)日：1998-10-13

申请号：US610563

申请日：1996-03-06

申请人： Fwu-Iuan Hshieh ,  Lih-Ying Ching ,  Hoang Tran ,  Mike F. Chang

发明人： Fwu-Iuan Hshieh ,  Lih-Ying Ching ,  Hoang Tran ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

摘要： A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub is formed surrounding the P+ body region in order to enhance avalanche breakdown. Thus the epitaxial layer resistivity can be decreased to reduce device on-resistance, while the desired breakdown voltage is also achieved. The on-resistance is further reduced by adding a pre-initial oxidation implant, i.e. phosphorous for an N channel device or boron for a P channel device. This forms a more heavily doped JFET or pinch region at the bottom of the trench and in the upper portion of the drift region. This N JFET region (which is P doped for a P channel device) is more heavily doped than the underlying epitaxial layer and surrounds the trench bottom, thus reducing on-resistance by increasing local doping concentration where otherwise a parasitic JFET would be present.

摘要翻译： 沟槽DMOS晶体管显着降低导通电阻。 形成围绕P +体区域的轻掺杂P桶，以增强雪崩击穿。 因此，可以减小外延层电阻率以减少器件导通电阻，同时也实现期望的击穿电压。 通过添加预初始氧化注入，即用于N沟道器件的磷或用于P沟道器件的硼，进一步降低导通电阻。 这在沟槽的底部和漂移区域的上部形成更重掺杂的JFET或夹持区域。 该N JFET区域（P掺杂用于P沟道器件）比下面的外延层更重掺杂并且围绕沟槽底部，从而通过增加局部掺杂浓度来降低导通电阻，否则将存在寄生JFET。

公开(公告)号：US5486772A

公开(公告)日：1996-01-23

申请号：US268755

申请日：1994-06-30

申请人： Fwu-Iuan Hshieh ,  Calvin K. Choi ,  William H. Cook ,  Lih-Ying Ching ,  Mike F. Chang

发明人： Fwu-Iuan Hshieh ,  Calvin K. Choi ,  William H. Cook ,  Lih-Ying Ching ,  Mike F. Chang

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L29/78

CPC分类号： G01R31/2621

摘要： The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the present invention, a negative voltage is applied to the gate of the trench transistor with its drain grounded and its source floating. A leakage current flowing between the gate and drain is measured as a function of the voltage applied to the gate. A transistor whose gate-drain leakage current exceeds a predetermined value at a specified gate voltage is deemed to be defective. In another embodiment of the present invention, the gate-drain leakage current is measured as described above and monitored over time. Charge accumulated near the gate-drain interface due to defects in the interface results in the gate-drain leakage current taking a longer period of time to fall off to its steady state value. Accordingly, if the leakage current of a particular trench transistor does not fall off to a predetermined value within a predetermined amount of time, the transistor is deemed to be defective. The minimum/maximum allowable gate-drain leakage current published in a data sheet for the trench transistor will provide consumers with additional assurance of the transistor's long term reliability.

摘要翻译： 本发明检测沟槽晶体管的栅极/沟槽表面界面附近的缺陷。 导致长期可靠性问题的接口附近的缺陷通常也会导致接口附近收费。 根据本发明的一个实施例，负电压被施加到沟槽晶体管的栅极，其漏极接地并且其源极漂移。 根据施加到栅极的电压来测量在栅极和漏极之间流动的漏电流。 栅极漏极泄漏电流在指定的栅极电压下超过预定值的晶体管被​​认为是有缺陷的。 在本发明的另一个实施例中，如上所述测量栅 - 漏泄漏电流并随时间监测。 由于界面缺陷，在栅极 - 漏极接口附近积聚的电荷导致栅极 - 漏极泄漏电流需要更长的时间来降低到其稳定状态值。 因此，如果特定沟槽晶体管的泄漏电流在预定时间内没有下降到预定值，则认为晶体管有缺陷。 在沟槽晶体管的数据手册中公布的最小/最大允许栅 - 漏泄漏电流将为消费者提供晶体管长期可靠性的额外保证。

公开(公告)号：US5629543A

公开(公告)日：1997-05-13

申请号：US537157

申请日：1995-08-21

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Lih-Ying Ching ,  Sze H. Ng ,  William Cook

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Lih-Ying Ching ,  Sze H. Ng ,  William Cook

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/0878 ,  H01L29/7813 ,  H01L29/1095

摘要： A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

摘要翻译： 沟槽DMOS晶体管包括在漏极区域和上覆漂移区域之间形成的具有与漂移区域和漏极区域相同的掺杂类型的掩埋层区域。 掩埋层区域比漏极区域或漂移区域更高掺杂，并且由例如， 在上覆漂移区域的外延生长之前的植入。 通过为掩埋层区域提供优化的掺杂分布，确保在掩埋层区域/体区发生雪崩击穿。 因此，消除了源极导通电阻，因为现有技术的器件中存在的JFET区域被消除，同时器件的耐用性和可靠性得到提高。

公开(公告)号：US5910669A

公开(公告)日：1999-06-08

申请号：US918954

申请日：1992-07-24

申请人： Mike F. Chang ,  Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  King Owyang

发明人： Mike F. Chang ,  Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  King Owyang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/4236

摘要： A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower epitaxial layer. The lightly doped upper epitaxial layer reduces the electric field at the bottom of the trench, thus protecting the gate oxide from breakdown during high voltage operation. Advantageously the upper portion of the lightly doped upper epitaxial layer has little adverse effect on the transistor's on resistance.

摘要翻译： 其栅电极位于沟槽中的DMOS场效应晶体管包括覆盖在通常外延层上的轻掺杂外延层。 沟槽仅穿过上层外延层的一部分，该外延层比下层的下层外延层更轻掺杂。 轻掺杂的上部外延层减小沟槽底部的电场，从而在高电压操作期间保护栅极氧化物不被击穿。 有利地，轻掺杂的上部外延层的上部对晶体管的导通电阻几乎没有不利影响。

公开(公告)号：US6069043A

公开(公告)日：2000-05-30

申请号：US962885

申请日：1997-11-12

申请人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L29/7722 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0847

摘要： A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

摘要翻译： 适合于低电压功率应用的沟槽场效应晶体管由于源极区和漏极区之间的栅极控制势垒区而提供低泄漏阻挡能力。 通过源极区域和漏极区域之间的反转区域发生正向导通。 封闭通过栅极控制的耗尽屏障实现。 位于源极和漏极区之间是相当轻掺杂的体区。 位于沟槽中的栅电极延伸穿过源极和体区，并且在一些情况下延伸到漏极区的上部。 多晶硅栅电极的掺杂剂类型与体区相同。 体区是在相对导电类型的高掺杂低电阻率衬底上生长的相对薄且轻掺杂的外延层。 在阻塞状态下，外延体区域由于施加的漏极 - 源极电压而耗尽，因此穿通型状态垂直发生。 横向栅极控制增加了大多数载流子的有效屏障，并将泄漏电流降低到可接受的低水平。

公开(公告)号：US5929481A

公开(公告)日：1999-07-27

申请号：US964419

申请日：1997-11-04

申请人： Fwu-Iuan Hshieh ,  Brian H. Floyd ,  Mike F. Chang ,  Danny Nim ,  Daniel Ng

发明人： Fwu-Iuan Hshieh ,  Brian H. Floyd ,  Mike F. Chang ,  Danny Nim ,  Daniel Ng

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/1095 ,  H01L29/0878 ,  H01L29/7813

摘要： A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions extending deeper than the trench) by providing a doped trench bottom implant region at the bottom of the trench and extending into the surrounding drift region. This trench bottom implant region has the same doping type, but is more highly doped, than the surrounding drift region. The trench bottom implant region significantly reduces the parasitic JFET resistance by optimizing the trench bottom implant dose, without creating reliability problems.

摘要翻译： 沟槽DMOS晶体管通过在沟槽的底部提供掺杂的沟槽底部注入区域并延伸到周围的漂移区域来克服沟槽底部的寄生JFET（由深沟槽深度延伸的深度）引起的问题。 该沟槽底部注入区域具有与周围漂移区域相同的掺杂类型，但是掺杂度更高。 通过优化沟槽底部注入剂量，沟槽底部注入区域显着降低寄生JFET电阻，而不会产生可靠性问题。

公开(公告)号：US5917216A

公开(公告)日：1999-06-29

申请号：US742326

申请日：1996-10-31

申请人： Brian H. Floyd ,  Dorman C. Pitzer ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Dorman C. Pitzer ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/7832

摘要： A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

摘要翻译： 其导通状态的沟槽MOSFET导通电流通过积聚区域并且穿过沿着沟槽侧壁设置的反向耗尽势垒层。 通过相邻区域的栅极控制耗尽和从沟槽侧壁横向延伸到其中的耗尽阻挡层（具有在截面图中的“耳朵”并且与相邻区域相反的掺杂类型）的外观来实现阻塞。 漂移区。 该MOSFET具有优于现有技术的沟槽MOSFET的导通电阻率，并且在导通状态电阻方面具有良好的性能，同时具有优于现有技术的沟槽MOSFET的阻塞特性。 阻挡特性的改善由作为半导体掺杂区域的耗尽阻挡层提供。 在阻挡状态下，耗尽阻挡层完全或几乎完全耗尽，以防止寄生双极导电。 可以改变耗尽阻挡层的形状和程度，并且可能存在多于一个的耗尽阻挡层。

公开(公告)号：US5592005A

公开(公告)日：1997-01-07

申请号：US415009

申请日：1995-03-31

申请人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L29/7722 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0847

摘要： A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

摘要翻译： 适合于低电压功率应用的沟槽场效应晶体管由于源极区和漏极区之间的栅极控制势垒区而提供低泄漏阻挡能力。 通过源极区域和漏极区域之间的反转区域发生正向导通。 封闭通过栅极控制的耗尽屏障实现。 位于源极和漏极区之间是相当轻掺杂的体区。 位于沟槽中的栅电极延伸穿过源极和体区，并且在一些情况下延伸到漏极区的上部。 多晶硅栅电极的掺杂剂类型与体区相同。 体区是在相对导电类型的高掺杂低电阻率衬底上生长的相对薄且轻掺杂的外延层。 在阻塞状态下，外延体区域由于施加的漏极 - 源极电压而耗尽，因此穿通型状态垂直发生。 横向栅极控制增加了大多数载流子的有效屏障，并将泄漏电流降低到可接受的低水平。

公开(公告)号：US5767578A

公开(公告)日：1998-06-16

申请号：US634957

申请日：1996-04-19

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

IPC分类号： H01L23/29 ,  H01L23/367 ,  H01L23/373 ,  H01L23/34

CPC分类号： H01L23/3672 ,  H01L23/29 ,  H01L23/3732 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 钝化层是提供电绝缘和导热性的CVD金刚石膜。 去除衬底背面（通过研磨和/或CMP）以暴露沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片以两种版本刻成模具，而不需要进一步的包装。

公开(公告)号：US5757081A

公开(公告)日：1998-05-26

申请号：US603512

申请日：1996-02-20

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/48

CPC分类号： H01L23/3672 ,  H01L23/3738 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/977

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 通过研磨或CMP去除衬底背面以露出沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片刻成两个版本的模具，无需进一步包装。