公开(公告)号：US09941271B2

公开(公告)日：2018-04-10

申请号：US14069174

申请日：2013-10-31

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Akira Ito

IPC: H01L27/10 ,  H01L21/70 ,  H01L27/088 ,  H01L27/06

CPC classification number: H01L27/0629

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

公开(公告)号：US09583613B2

公开(公告)日：2017-02-28

申请号：US14625047

申请日：2015-02-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Shom Ponoth

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7824 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/78624

Abstract: A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.

Abstract translation: 半导体器件包括设置在半导体衬底中的第一阱。 半导体器件还包括设置在半导体衬底中的第二阱。 半导体器件还包括在源极区域和漏极区域之间的源极区域，漏极区域和栅极结构。 栅极结构设置在第一阱的上方。 源极区包括在第一阱上方的第一导电接触。 漏极区域包括在第二阱上方的第二导电接触，漏极区域至少部分地通过第一外延区域与第二阱连接。 第一外延区域和第二阱被配置为将施加在源极区域和漏极区域上的第一驱动电压降低到施加在栅极结构上的第二电压。

公开(公告)号：US09520398B1

公开(公告)日：2016-12-13

申请号：US14818280

申请日：2015-08-04

Applicant: BROADCOM CORPORATION

Inventor： Akira Ito

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/761 ,  H01L21/823892 ,  H01L29/1083 ,  H01L29/7833

Abstract: A device includes a substrate, a deep well, a first well, and a second well. The deep well is formed in the substrate. The first well includes a first portion formed on the deep well and a second portion formed in the substrate. The second well is formed partially on the deep well. A first separator structure is formed on the deep well to isolate the first portion of the first well from the second well, and a second separator structure is formed on the substrate to isolate the second well and a second portion of the first well.

Abstract translation: 一种装置包括基底，深井，第一井和第二井。 在衬底中形成深阱。 第一阱包括形成在深阱上的第一部分和形成在衬底中的第二部分。 第二口井部分形成在深井上。 在深井上形成第一分离器结构以将第一井的第一部分与第二井隔离，并且在衬底上形成第二分离器结构以隔离第二井和第一井的第二部分。

公开(公告)号：US09472615B2

公开(公告)日：2016-10-18

申请号：US14598119

申请日：2015-01-15

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Akira Ito

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/0634 ,  H01L29/063 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/6681 ,  H01L29/7823 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a top surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the top surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the top surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

Abstract translation: 提供了一种鳍状场效应晶体管（finFET）器件。 finFET器件包括具有顶表面和底表面的衬底材料。 finFET器件还包括形成在衬底材料中的阱区。 阱区可以包括第一类型的掺杂剂。 finFET器件还包括设置在衬底材料的顶表面上的翅片结构。 翅片结构的一部分可以包括第一类型的掺杂剂。 finFET器件还包括设置在衬底材料的顶表面上并且与鳍结构的部分相邻的氧化物材料。 finFET器件还包括设置在鳍结构的一部分上的第一外延材料。 第一外延材料可以包括第二类型的掺杂剂。

公开(公告)号：US09379236B2

公开(公告)日：2016-06-28

申请号：US14309843

申请日：2014-06-19

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Akira Ito

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

Abstract: A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.

Abstract translation: 用于高电压操作的横向双扩散MOS（LDMOS）体鳍鳍FETFET器件包括形成在衬底材料上的第一阱区域和两个或更多个第二阱区域以及包括衬底材料的一个或多个非阱区域。 非阱区域被配置为分离第二阱区域的阱区域。 源结构设置在部分地形成在第一阱区上的第一鳍上。 漏极结构设置在形成在第二阱区域的最后一个上的第二鳍片上。 在一个或多个非阱区域上形成一个或多个虚拟区域。 虚拟区域被配置为提供额外的耗尽区域流动路径，包括用于电荷载体的垂直流动路径以实现高电压操作。

公开(公告)号：US09190501B2

公开(公告)日：2015-11-17

申请号：US13800063

申请日：2013-03-13

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Kenneth Yau

IPC: H01L29/66 ,  H01L29/735 ,  H01L29/08 ,  H01L29/739

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/739

Abstract: A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate. The collector region is implanted in the semiconductor substrate. The base region is disposed between the emitter region and collector region. The base region includes no more than one LDD region and no more than one halo region. The base region contacts directly with at least one of the emitter region and the collector region.

Abstract translation: 半导体器件包括发射极区域，集电极区域和基极区域。 发射极区域被注入到半导体衬底中。 集电极区域被注入到半导体衬底中。 基极区域设置在发射极区域和收集极区域之间。 碱性区域包括不超过一个LDD区域和不多于一个卤素区域。 基极区域与发射极区域和集电极区域中的至少一个直接接触。

公开(公告)号：US08969957B2

公开(公告)日：2015-03-03

申请号：US13945739

申请日：2013-07-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Xiangdong Chen

IPC: H01L21/70 ,  H01L23/52 ,  H01L29/78 ,  H01L27/112 ,  H01L23/525 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US20140239451A1

公开(公告)日：2014-08-28

申请号：US13800063

申请日：2013-03-13

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Kenneth Yau

IPC: H01L29/735 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/739

Abstract: A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate. The collector region is implanted in the semiconductor substrate. The base region is disposed between the emitter region and collector region. The base region includes no more than one LDD region and no more than one halo region. The base region contacts directly with at least one of the emitter region and the collector region.

Abstract translation: 半导体器件包括发射极区域，集电极区域和基极区域。 发射极区域被注入到半导体衬底中。 集电极区域被注入到半导体衬底中。 基极区域设置在发射极区域和收集极区域之间。 碱性区域包括不超过一个LDD区域和不多于一个卤素区域。 基极区域与发射极区域和集电极区域中的至少一个直接接触。

公开(公告)号：US20140167173A1

公开(公告)日：2014-06-19

申请号：US13715740

申请日：2012-12-14

Applicant: BROADCOM CORPORATION

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device includes a first well, a second well, and a separator structure. The first well and the second well are implanted in the semiconductor substrate. The separator structure is also implanted in the semiconductor substrate and separates the first well and the second well so that the first well and the second well do not contact each other.

Abstract translation: 半导体器件包括第一阱，第二阱和分离器结构。 将第一阱和第二阱注入到半导体衬底中。 分离器结构也被注入到半导体衬底中并分离第一阱和第二阱，使得第一阱和第二阱不彼此接触。

公开(公告)号：US09379212B1

公开(公告)日：2016-06-28

申请号：US14611134

申请日：2015-01-30

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Shom Surendran Ponoth ,  Akira Ito

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L23/66

CPC classification number: H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/28114 ,  H01L23/66 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

Abstract translation: 具有增加的漏极 - 源极电压（Vds）的MOS器件包括沉积在衬底上的源极区域和漏极区域。 栅极区域包括延伸漏极区域的内部间隔物。 内部间隔件形成附接到隔离间隔件，隔离间隔件将漏极区域与栅极区域隔离。 内部间隔件被配置为延伸漏极区域以修改MOS器件的导电带的一部分中的电场。