-
公开(公告)号：US20120284543A1
公开(公告)日：2012-11-08
申请号：US13099077
申请日：2011-05-02
CPC分类号： G06F1/3203 , G06F1/3206
摘要： Techniques for user input triggered device power management are described that enable user inputs and activities to cause selective changes in power states for a device. Power can be boosted to a high power state to improve responsiveness for designated inputs and/or activities. When responsiveness is deemed less important in connection with particular inputs and/or activities, a low power state can be set to reduce energy consumption. In at least some embodiments, selectively switching between power states includes detecting various user inputs at a device and filtering the inputs to select power states associated with the user inputs. The device can then be operated in a selected power state until a transition to a different power state is triggered by occurrence of designated events, such as running of a set time interval, further user input, and/or completion of user activity.
摘要翻译： 描述用于用户输入触发的设备电源管理的技术，其使得用户输入和活动能够引起对设备的功率状态的选择性改变。 电力可以提升到高功率状态，以提高对指定投入和/或活动的响应能力。 当响应性被认为与特定输入和/或活动相关的重要性较低时，可以设置低功率状态以降低能量消耗。 在至少一些实施例中，选择性地在功率状态之间切换包括检测设备处的各种用户输入并且过滤输入以选择与用户输入相关联的功率状态。 然后可以以所选择的功率状态操作设备，直到通过发生指定事件（例如运行设定的时间间隔，进一步的用户输入和/或用户活动的完成）触发到不同功率状态的转换。
-
公开(公告)号：US20110145609A1
公开(公告)日：2011-06-16
申请号：US12636732
申请日：2009-12-12
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/126
摘要： A computer system may place memory objects in specific memory physical regions based on energy consumption and performance or other policies. The system may have multiple memory regions at least some of which may be powered down or placed in a low power state during system operation. The memory object may be characterized in terms of access frequency, movability, and desired performance and placed in an appropriate memory region. In some cases, the memory object may be placed in a temporary memory region and later moved to a final memory region for long term placement. The policies may allow some processes to operate while consuming less energy, while other processes may be configured to maximize performance
摘要翻译： 计算机系统可以基于能量消耗和性能或其他策略将存储器对象放置在特定存储器物理区域中。 系统可以具有多个存储器区域，其中至少一些可以在系统操作期间被掉电或置于低功率状态。 可以根据访问频率，可移动性和期望的性能来表征存储器对象，并将其放置在适当的存储器区域中。 在一些情况下，存储器对象可以被放置在临时存储器区域中，并且随后被移动到最终存储器区域以进行长期放置。 这些策略可以允许一些进程在消耗更少的能量的同时运行，而其他进程可以被配置为使性能最大化
-
公开(公告)号：US20110093726A1
公开(公告)日：2011-04-21
申请号：US12579524
申请日：2009-10-15
CPC分类号： G06F1/3275 , G06F1/3225 , G06F12/06 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A computer system may manage objects in memory to consolidate less frequently accessed objects into memory regions that may be operated in a low power state where the access times may increase for the memory objects. By operating at least some of the memory regions in a low power state, significant power savings can be realized. The computer system may have several memory regions that may be independently controlled and may move memory objects to various memory regions in order to optimize power consumption. In some embodiments, an operation system level function may manage memory objects based on parameters gathered from usage history, memory topology and performance, and input from applications.
摘要翻译： 计算机系统可以管理存储器中的对象，以将较不频繁访问的对象合并到可以在存储器对象的访问时间可能增加的低功率状态下操作的存储器区域中。 通过在低功率状态下操作至少一些存储器区域，可以实现显着的功率节省。 计算机系统可以具有可独立控制的几个存储区域，并且可以将存储器对象移动到各种存储器区域，以便优化功耗。 在一些实施例中，操作系统级功能可以基于从使用历史，存储器拓扑和性能以及来自应用的输入收集的参数来管理存储器对象。
-
公开(公告)号：US20090327555A1
公开(公告)日：2009-12-31
申请号：US12147455
申请日：2008-06-26
IPC分类号： G06F13/24
CPC分类号： G06F13/26
摘要： Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device.
摘要翻译： 描述处理器中断确定程序。 在一个实现中，一个或多个计算机可读介质包括可由计算机执行的指令，以便基于性能目标来确定多个处理器中的哪个处理器将被要执行输入/输出操作的设备 当发现来自设备的中断消息并且针对确定的处理器时。 中断消息被传送到设备以指示所确定的处理器的可用性以供设备使用。 当与多个处理器中的其他处理器相比较时，当发现来自设备的中断消息并且与所确定的处理器附近的替代处理器相对准时，将针对替代处理器的中断消息传送到设备以指示可用性 替代处理器由设备使用。
-
公开(公告)号：US08024504B2
公开(公告)日：2011-09-20
申请号：US12147455
申请日：2008-06-26
CPC分类号： G06F13/26
摘要： Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device.
摘要翻译： 描述处理器中断确定程序。 在一个实现中，一个或多个计算机可读介质包括可由计算机执行的指令，以便基于性能目标来确定多个处理器中的哪个处理器将被要执行输入/输出操作的设备 当发现来自设备的中断消息并且针对确定的处理器时。 中断消息被传送到设备以指示所确定的处理器的可用性以供设备使用。 当与多个处理器中的其他处理器相比较时，当发现来自设备的中断消息并且与所确定的处理器附近的替代处理器相对准时，将针对替代处理器的中断消息传送到设备以指示可用性 替代处理器由设备使用。
-
公开(公告)号：US20110022870A1
公开(公告)日：2011-01-27
申请号：US12506687
申请日：2009-07-21
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3293 , G06F9/5094 , G06F11/3006 , G06F11/301 , G06F11/3062 , G06F11/3433 , Y02D10/122 , Y02D10/126 , Y02D10/22 , Y02D10/34
摘要： A component level power monitoring system may analyze workloads by determining energy consumed by individual components for the workload. By comparing different system configurations or by modifying the software operation, an optimized workload may be performed per energy consumed. In some embodiments, several system configurations may be attempted to determine an optimized system configuration. In other embodiments, a monitoring system may change how an application is executed by changing thread affinity or otherwise assigning certain operations to specific components. The component level monitoring may be implemented as operating system level function calls.
摘要翻译： 组件级电源监控系统可以通过确定各个组件为工作负载消耗的能量来分析工作负载。 通过比较不同的系统配置或通过修改软件操作，可以对每消耗的能量执行优化的工作负载。 在一些实施例中，可以尝试若干系统配置来确定优化的系统配置。 在其他实施例中，监视系统可以通过改变线程相关性或以其他方式将特定操作分配给特定组件来改变应用程序的执行方式。 组件级监视可以被实现为操作系统级功能调用。
-
公开(公告)号：US20090327556A1
公开(公告)日：2009-12-31
申请号：US12163057
申请日：2008-06-27
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Processor selection procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable to cause a processor executing the instructions to select, based on a performance goal, which of a plurality of processors is to further handle a device interrupt and when the selected processor is available, notify the selected processor to further handle the device interrupt.
摘要翻译： 描述处理器选择过程。 在实现中，一个或多个计算机可读介质包括可执行以使处理器执行指令的指令，其基于性能目标，选择多个处理器中的哪一个来进一步处理设备中断，并且当所选择的处理器 可用，通知所选择的处理器进一步处理设备中断。
-
公开(公告)号：US08495299B2
公开(公告)日：2013-07-23
申请号：US12619571
申请日：2009-11-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F12/0893
摘要： A cache controller in a computer system is configured to manage a cache. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.
摘要翻译： 计算机系统中的高速缓存控制器被配置为管理高速缓存。 缓存控制器从处理器接收命令。 作为响应，修改了针对高速缓存中的每个块的维护信息的高速缓存映射。 高速缓存映射可以包括每个高速缓存块的地址，脏位，零位和优先级。 该地址指示高速缓存块高速缓存数据的主存储器中的地址。 脏位指示高速缓存块中的数据是否与地址中主存储器中的数据一致。 零位表示地址中的数据是否应被读取为默认值，优先级指定用于逐出缓存块的优先级。 通过操纵该映射信息，可以实现诸如移动，复制交换，零，优先化和停用之类的命令。
-
公开(公告)号：US08321703B2
公开(公告)日：2012-11-27
申请号：US12636732
申请日：2009-12-12
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/126
摘要： A computer system may place memory objects in specific memory physical regions based on energy consumption and performance or other policies. The system may have multiple memory regions at least some of which may be powered down or placed in a low power state during system operation. The memory object may be characterized in terms of access frequency, movability, and desired performance and placed in an appropriate memory region. In some cases, the memory object may be placed in a temporary memory region and later moved to a final memory region for long term placement. The policies may allow some processes to operate while consuming less energy, while other processes may be configured to maximize performance.
摘要翻译： 计算机系统可以基于能量消耗和性能或其他策略将存储器对象放置在特定存储器物理区域中。 系统可以具有多个存储器区域，其中至少一些可以在系统操作期间被掉电或置于低功率状态。 可以根据访问频率，可移动性和期望的性能来表征存储器对象，并将其放置在适当的存储器区域中。 在一些情况下，存储器对象可以被放置在临时存储器区域中，并且随后被移动到最终存储器区域以进行长期放置。 这些策略可以允许一些进程在消耗更少的能量的同时运行，而其他进程可以被配置为使性能最大化。
-
20.发明申请MANAGING MEMORY WITH LIMITED WRITE CYCLES IN HETEROGENEOUS MEMORY SYSTEMS 有权在异质存储器系统中管理具有有限写入周期的存储器公开(公告)号：US20120117304A1
公开(公告)日：2012-05-10
申请号：US12940780
申请日：2010-11-05
CPC分类号： G06F11/3037 , G06F11/3055 , G06F12/0223 , G06F12/06 , G06F2212/205 , G11C16/349
摘要： A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.
摘要翻译： 一种用于管理多种类型的存储器中的数据存储的方法和存储器管理器。 存储器的类型可以包括诸如DRAM的主存储器，以及可能具有有限寿命的次要存储器，例如相变存储器（PCM）或闪速存储器。 存储器管理器可以是操作系统的一部分，并且可以作为统一地址空间的一部分来管理存储器。 要存储在存储器中的数据的特征可以用于在主存储器和次存储器之间选择存储数据并在存储器之间移动数据。 当数据要存储在辅助存储器中时，辅助存储器上的健康信息和要存储的数据的特性可以用于选择次存储器内的存储数据的位置。
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.033 秒)
