公开(公告)号：US20060114042A1

公开(公告)日：2006-06-01

申请号：US11286686

申请日：2005-11-23

Applicant: Heon-soo Lee ,  Byeong-hoon Lee

Inventor： Heon-soo Lee ,  Byeong-hoon Lee

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03K5/086

Abstract: There is provided a compact duty cycle correction circuit including minimal components for generating a signal with a 50% duty cycle. The duty cycle correction circuit includes a storage element and a correction circuit. The storage element generates an output signal in response to a clock signal and a feedback signal. The correction circuit includes a resistor and a capacitor and outputs the feedback signal in response to the output signal of the storage element.

Abstract translation: 提供了一种紧凑的占空比校正电路，其包括用于产生具有50％占空比的信号的最小组件。 占空比校正电路包括存储元件和校正电路。 存储元件响应于时钟信号和反馈信号产生输出信号。 校正电路包括电阻器和电容器，并且响应于存储元件的输出信号而输出反馈信号。

公开(公告)号：US20080195916A1

公开(公告)日：2008-08-14

申请号：US12010244

申请日：2008-01-23

Applicant: Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G11C29/00

CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0411

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.

Abstract translation: 示例性实施例提供了一种在包括多个存储器单元的非易失性存储器件内由于电荷损失而校正误差数据的方法和装置。 校正非易失性存储器件中的错误数据的方法可以包括通过将响应于第一电压的存储器单元读取的第一数据组与从存储器单元读取的第二数据组进行响应来检测第二数据组中的错误数据 到第二电压。 第二电压高于第一电压。 通过纠错码（ECC）检测第一数据组中的错误数据。 通过对第一数据组中的错误数据和第二数据组中的错误数据进行校正，来重新写入存储器单元中的数据。 中央处理单元（CPU）可以检测第二数据组中的错误。 可以通过页缓冲器读取第二数据组，并与存储在SRAM中的第一数据组进行比较。 检测到的错误可能更新到页面缓冲区。 第一个数据组中的错误数据可能更新到页面缓冲区。 CPU更正最终错误数据中的错误，并且页缓冲区重写多个存储单元中的校正数据。

公开(公告)号：US20080183954A1

公开(公告)日：2008-07-31

申请号：US12016680

申请日：2008-01-18

Applicant: Seung-won LEE ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won LEE ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G06F12/02

CPC classification number: G06F13/4239

Abstract: An apparatus and method for controlling an embedded NAND flash memory. The apparatus includes a code memory storing code information for controlling an access to a NAND flash memory. A register stores code information corresponding to a command to be executed by the NAND flash memory. A central processing unit (CPU) reads the code information corresponding to the command to be executed by the NAND flash memory from the code memory and stores the read code information in the register. A hard-wired logic circuit performs the NAND flash memory access according to the code information stored in the register.

Abstract translation: 一种用于控制嵌入式NAND闪速存储器的装置和方法。 该装置包括存储用于控制对NAND快闪存储器的访问的代码信息的代码存储器。 寄存器存储与由NAND闪存执行的命令对应的代码信息。 中央处理单元（CPU）从代码存储器读取与NAND闪存要执行的命令对应的代码信息，并将读取的代码信息存储在寄存器中。 硬接线逻辑电路根据存储在寄存器中的代码信息执行NAND闪速存取存取。

公开(公告)号：US20060139073A1

公开(公告)日：2006-06-29

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US07030707B2

公开(公告)日：2006-04-18

申请号：US10859622

申请日：2004-06-03

Applicant: Byeong-hoon Lee ,  Sun-kwon Kim

Inventor： Byeong-hoon Lee ,  Sun-kwon Kim

IPC: H03B5/24 ,  H03K3/027 ,  H03L1/00

CPC classification number: H03K3/0231 ,  G06F1/08 ,  G11C16/30

Abstract: An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.

Abstract translation: 振荡器包括比较电压产生电路，比较电路和时钟切换电路。 比较电压产生电路由电源电压驱动，并产生响应于具有与电源电压和第一参考电压成反比变化的频率的时钟信号而变化的比较电压。 比较电路将比较电压的电平与第二参考电压进行比较，并输出具有作为比较结果的逻辑电平的逻辑信号。 时钟切换电路响应于逻辑信号输出具有与电源电压成反比变化的频率的时钟信号。

公开(公告)号：US20050007201A1

公开(公告)日：2005-01-13

申请号：US10859622

申请日：2004-06-03

Applicant: Byeong-hoon Lee ,  Sun-kwon Kim

Inventor： Byeong-hoon Lee ,  Sun-kwon Kim

IPC: H03K3/354 ,  G06F1/08 ,  G11C16/30 ,  H03K3/0231 ,  H03L7/00

CPC classification number: H03K3/0231 ,  G06F1/08 ,  G11C16/30

Abstract: An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.

Abstract translation: 振荡器包括比较电压产生电路，比较电路和时钟切换电路。 比较电压产生电路由电源电压驱动，并产生响应于具有与电源电压和第一参考电压成反比变化的频率的时钟信号而变化的比较电压。 比较电路将比较电压的电平与第二参考电压进行比较，并输出具有作为比较结果的逻辑电平的逻辑信号。 时钟切换电路响应于逻辑信号输出具有与电源电压成反比变化的频率的时钟信号。