Abstract:
Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.
Abstract:
Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.
Abstract:
An apparatus and method for controlling an embedded NAND flash memory. The apparatus includes a code memory storing code information for controlling an access to a NAND flash memory. A register stores code information corresponding to a command to be executed by the NAND flash memory. A central processing unit (CPU) reads the code information corresponding to the command to be executed by the NAND flash memory from the code memory and stores the read code information in the register. A hard-wired logic circuit performs the NAND flash memory access according to the code information stored in the register.
Abstract:
An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.
Abstract:
An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.
Abstract:
A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.
Abstract:
A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.
Abstract:
Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal.
Abstract:
An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.
Abstract:
Methods and apparatuses for changing capacitance are provided. The apparatus may adjust a current supplied to a load capacitor according to the frequency of an input clock signal. When operating at a lower frequency, a capacitance may be increased such that noise immunity may be increased. When operating at a higher frequency, a capacitance may be decreased such that current consumption may be reduced.